Publications by Didier Bouvet | EPFL Graph Search

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In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80 nm Si cores on bulk Si using 0.8 mu m optical lithography and local oxidation for the first time. 0.833 GPa uniaxial tensile stress is measured in the buckled s ...

This work reports on memory applications of punch-through impact ionization single-transistor latch (PIMOS), showing abrupt current switching (3-10mV/dec.) as well as hysteresis in both ID(VDS) and ID(VGS). A capacitor-less 1PIMOS - 1 MOSFET DRAM memory is ...

In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5 ...

The performance of a standard MOSFET degrades with the increase in temperature, impacting the power consumption of the device. In this paper, we report the opposite trend, which is reflected in an improvement of main performance factors in ferroelectric FE ...

The effects of extreme radiation levels on the electrical resistivity of metal thin films made of copper were studied by means of electrical measurements and post irradiation imaging. Different 3x3 mm(2) chips were produced by depositing 500 nm of meander ...

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using mu ...

In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode nMOSFETs with sub-5 nm cross-sections. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ≥ 2.5 GPa uniaxial tensile stress is reported for the first time. The deeply scaled Si nanowire shows low-field electron mobility of 332 cm2/V.s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as h

We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells. We report I-on/I-off larger than 10(5) and I-off on the order of 100 fA/mu m in micrometer-scale p-type Fe-TFETs fabricated on ultrathin-film (fully depleted) sili

This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60 mV/decade subthreshold swing limit at room temperature of MOSFET ...

This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the r ...

In this work we report an experimental study on accumulation-mode (AM) gate-all-around (GAA) nMOSFETs based on silicon nanowires with uniaxial tensile strain. Their electrical characteristics are studied from room temperature up to ~400 K and carrier mobility, flat-band and threshold voltages are extracted and investigated.

An attractive combination of properties of the ferroelectric copolymer of vinylidene fluoride and trifluoroethylene (P(VDF-TrFE)), including a relatively high spontaneous polarization and low dielectric constant as well as low processing temperature makes this material useful for studying the ferroelectric gate operation for 1T nonvolatile ferroelecetric memory applications. Here we explore a silicon-based ferroelectric field effect transistor with P(VDF-TrFE) gate showing a persistent switching of the drai

A polymer based Ferroelectric gate FET at 1T non-volatile memory on bulk silicon is demonstrated. Spin-coated 40 nm and 100 nm P(VDF-TrFE) (70%-30%) ultra-thin films have been integrated onto 10 nm SiO₂ layer as gate dielectric into a conventional silicon ...

In this letter, an abrupt NMOS inverter based on punch-through impact ionization is demonstrated for the first time. The slopes for both the rising and the falling edge of the ID(V GS) device characteristics are less than 10 mV/dec ...

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowi ...

This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching ...

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drai ...

In this paper, we demonstrate the integration of local oxidation and metal-gate strain technologies to induce 3.3%/5.6 GPa uniaxial tensile strain/stress in 2 μm long suspended Si nanowire MOSFETs, the highest process-based stress record in MOSFETs until now, by elastic local buckling. Significant stress level modulation in the channel from 1.2 to 5.6 GPa on a single wafer is demonstrated for the first time by varying the NW width. The GAA Si NW MOSFET with 5.6 GPa uniaxial tensile stress is characterized a

We report for the first time the optimization of the channel lateral strain profile as a new technological booster for improved performance of multi-gate n-channel MOSFET. We find that quasi-uniform or flat-Gaussian-close-to-the-drain profiles are optimum for the Ion boosting of sub-50nm scaled MOSFETs, while the penalty on Ioff and subthreshold slope is minimum. The reported predictions use realistic lateral uniaxial strain profiles, with peaks up to few GPa's and average values of hundreds of MPa's. ©2009

Didier Bouvet

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Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic

DRAM Based on Hysteresis in Impact Ionization Single-Transistor-Latch

Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

Modeling the Temperature Dependence of Fe-FET Static Characteristics Based on Landau's Theory

Radiation enhanced oxidation of proton-irradiated copper thin-films: Towards a new concept of ultra-high radiation dosimetry

Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays

Accumulation-Mode GAA Si NW nFET with sub-5 nm cross-section and high uniaxial tensile strain

The Hysteretic Ferroelectric Tunnel FET

Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO₂ gate stack

Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

Ferroelectric Polymer Gate Transistor as a Model System for Exploring the Mechanisms of the Retention Loss

Low voltage Ferroelectric FET with sub-100nm copolymer P(VDF-TrFE) gate dielectric for non-volatile 1T memory

Abrupt NMOS Inverter Based on Punch-Through Impact Ionization With Hysteresis in the Voltage Transfer Characteristics

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling

Electrical conduction in 10 nm thin polysilicon wires from 4 to 400 K and their operation for hybrid memory

Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs