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Didier Bouvet

Cette personne a quitté l’EPFL

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Publications associées (57)

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Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

Mihai Adrian Ionescu, Jean-Michel Sallese, Didier Bouvet, Mohammad Najmzadeh, Wladyslaw Grabinski

In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5 ...

Elsevier2012

Radiation enhanced oxidation of proton-irradiated copper thin-films: Towards a new concept of ultra-high radiation dosimetry

Jean-Michel Sallese, Didier Bouvet, Georgi Gorine

The effects of extreme radiation levels on the electrical resistivity of metal thin films made of copper were studied by means of electrical measurements and post irradiation imaging. Different 3x3 mm(2) chips were produced by depositing 500 nm of meander ...

2019

Modeling the Temperature Dependence of Fe-FET Static Characteristics Based on Landau's Theory

Mihai Adrian Ionescu, Didier Bouvet, Livio Lattanzio, Giovanni Antonio Salvatore

The performance of a standard MOSFET degrades with the increase in temperature, impacting the power consumption of the device. In this paper, we report the opposite trend, which is reflected in an improvement of main performance factors in ferroelectric FE ...

2011

Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays

Mihai Adrian Ionescu, Giovanni De Micheli, Yusuf Leblebici, David Atienza Alonso, Didier Bouvet, Kirsten Emilie Moselund, Mohamed Haykel Ben Jamaa

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using mu ...

2007

Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO₂ gate stack

Mihai Adrian Ionescu, Didier Bouvet, Giovanni Antonio Salvatore

This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60 mV/decade subthreshold swing limit at room temperature of MOSFET ...

2008

Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology

Jean-Michel Sallese, Didier Bouvet, Lucian Barbut

This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the r ...

IEEE2011

Electrochemically controlled wear transitions in the tribocorrosion of ruthenium

Michel Declercq, Didier Bouvet, Stefano Mischler

This work presents an investigation of the tribocorrosion of ruthenium in sulphuric acid solutions. The study was focused on the effect of the electrode potential on wear of ruthenium during sliding against an inert alumina ball in a reciprocating sliding ...

2009

Influence of chelating agents on the tribocorrosion of tungsten in sulphuric acid solution

Michel Declercq, Didier Bouvet, Stefano Mischler

The corrosion and tribocorrosion of tungsten in 0.01 M H2SO4, without and with the presence of lactic acid and phosphoric acid as chelating agents was studied here. ...

2011

Low voltage Ferroelectric FET with sub-100nm copolymer P(VDF-TrFE) gate dielectric for non-volatile 1T memory

Mihai Adrian Ionescu, Nava Setter, Didier Bouvet, Igor Stolichnov, Giovanni Antonio Salvatore

A polymer based Ferroelectric gate FET at 1T non-volatile memory on bulk silicon is demonstrated. Spin-coated 40 nm and 100 nm P(VDF-TrFE) (70%-30%) ultra-thin films have been integrated onto 10 nm SiO₂ layer as gate dielectric into a conventional silicon ...

2008

Abrupt NMOS Inverter Based on Punch-Through Impact Ionization With Hysteresis in the Voltage Transfer Characteristics

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund

In this letter, an abrupt NMOS inverter based on punch-through impact ionization is demonstrated for the first time. The slopes for both the rising and the falling edge of the ID(V GS) device characteristics are less than 10 mV/dec ...

Institute of Electrical and Electronics Engineers2008

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

Jean-Michel Sallese, Farzan Jazaeri, Didier Bouvet, Lucian Barbut

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowi ...

Institute of Electrical and Electronics Engineers2014

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott

This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching ...

2008

Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

Jean-Michel Sallese, Farzan Jazaeri, Didier Bouvet, Lucian Barbut

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drai ...

2013

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

Mihai Adrian Ionescu, Didier Bouvet, Mohammad Najmzadeh, Wladyslaw Grabinski

In this paper, we report for the first time making multi-gate buckled self-aligned dual Si nanowires including two sub-100 nm cross-section cores on bulk Si substrate using optical lithography, hard mask/spacer technology and local oxidation. 0.8 GPa uniax ...

Institute of Electrical and Electronics Engineers2012

Electrical conduction in 10 nm thin polysilicon wires from 4 to 400 K and their operation for hybrid memory

Mihai Adrian Ionescu, Didier Bouvet, Santanu Mahapatra, Serge Ecoffey

2006

Co-integration of gate-all-around MOSFETs and local silicon-on insulator optical waveguides on bulk silicon for GHz on-chip optical signaling

Mihai Adrian Ionescu, Romuald Houdré, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott, Nicolas Le Thomas

2006

Low temperature investigation of electrical conduction in polysilicon: simulation and experiment

Mihai Adrian Ionescu, Didier Bouvet, Vincent Pott, Santanu Mahapatra, Serge Ecoffey

2005

Transient Off-Current in Junctionless FETs

Jean-Michel Sallese, Farzan Jazaeri, Didier Bouvet, Lucian Barbut

We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless fieldeffect transistors. This effect might be attributed to a process involving generati ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Transient current technique for charged traps detection in silicon bonded interfaces

Jean-Michel Sallese, Alessandro Mapelli, Didier Bouvet

Wafer bonding is an established technology for the manufacturing of silicon-on-insulator (SOI) substrates, microelectromechanical systems (MEMS) and microfluidic devices. Low temperature direct bonding techniques can be of particular interest for the fabri ...

2019

New Logic Family Based on Hybrid MOSFET-Polysilicon Nano-Wires

Mihai Adrian Ionescu, Yusuf Leblebici, Alexandre Schmid, Michel Declercq, Didier Bouvet, Vincent Pott, Marco Mazza, Serge Ecoffey

2005