Publication

Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

Jean-Michel Sallese, Farzan Jazaeri, Didier Bouvet, Lucian Barbut
2013
Conference Papers

Abstract

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drain induced barrier lowering is investigated with respect to the technological parameters. This work could serve as a guideline for technology optimization and design of JL VeSFETs.

Official source

https://infoscience.epfl.ch/entities/publication/73a8fd07-2e1b-47d7-8245-a0dd5510d30a

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Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

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