Publications de Andreas Peter Burg

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Centralized radio access networks (C-RAN) are widely recognized as an enabling technology for the evolution of cellular systems, including 5G and beyond. However, the concept is not limited to 3GPP cellular systems and licensed frequency bands. In recent y ...

In-band full-duplex systems can transmit and receive information simultaneously and on the same frequency band. However, due to the strong self-interference caused by the transmitter to its own receiver, the use of non-linear digital self-interference canc ...

We present an LLR-based implementation of the successive cancellation list (SCL) decoder. To this end, we associate each decoding path with a metric which (i) is a monotone function of the path’s likelihood and (ii) can be computed efﬁciently from the chan ...

Low-Density Parity-Check (LDPC) decoder is among the power hungry building blocks of wireless communication systems. Voltage scaling down to Near-Threshold (NT) voltages substantially improves energy efficiency, in theory up 10x. However, tuning the voltag ...

We present a doubly parallelized layered quasi-cyclic low density parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard. The decoding algorithm is equivalent to a nonparallelized layered decoder and, thus, retains its favorable ...

We describe the VLSI implementation of MIMO detectors that exhibit close-to optimum error-rate performance, but still achieve high throughput at low silicon area. In particular algorithms and VLSI architectures for sphere decoding (SD) and K-best detection ...

Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configur ...

Due to its high parallelism, belief propagation (BP)decoding is amenable to high-throughput applications and thusrepresents a promising solution for the ultra-high peak datarate required by future communication systems. To bridge theperformance gap compare ...

Millimeter wave (mmWave) communication is a promising solution for coping with the ever-increasing mobile data traffic because of its large bandwidth. To enable a sufficient link margin, a large antenna array employing directional beamforming, which is ena ...

Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is an emerging alternative to conventional SRAM for memory-dominated system-on-chip (SoC) designs due to its high-density, low-power, and two-ported operation. Although GCs have a limited data retention t ...

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access lim ...

Mobile network operators constantly have to upgrade their cellular network to satisfy the public's hunger for increasing data capacity. However, regulatory limits regarding allowed electromagnetic field strength on existing cell sites often limit or preven ...

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

Next generation wireless local area networks (WLANs) such as the IEEE 802.11n standard are expected to rely on multiple antennas at both transmitter and receiver to increase throughput and link reliability. However, these improvements come at a significant ...

Energy in today's short-range wireless communication is mostly spent on the analog-and digital hardware rather than on radiated power. Hence, purely information-theoretic considerations fail to achieve the lowest energy per information bit and the optimiza ...

Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efﬁciency in wireless communications. In this paper we present the—to the best of our know ...

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT

Audio processing had been in demand throughout the electronic era. Recent advances in neural networks increased the demand on audio processing for speech recognition applications. In this work, a rigorous study on the dynamic range and system complexity op ...

The impact of supply voltage scaling on the retention time of a 2-transistor (2T) gain-cell (GC) storage array is investigated, in order to enable low-power/low-voltage data storage. The retention time can be increased when scaling down the supply voltage ...

Andreas Peter Burg

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Centralized RAN for LPWAN: Architecture and Proof-of-Concept Prototype Implementation

Hardware Implementation of Neural Self-Interference Cancellation

LLR-based Successive Cancellation List Decoding of Polar Codes

Low Power LDPC Decoding by Reliable Voltage Down-Scaling

A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad

Advanced receiver algorithms for MIMO wireless communications

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes

Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique

Beam Selection and Tracking for Amplify-and-Forward Repeaters

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs

Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems

A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Dynamic Range and Complexity Optimization of Mixed-Signal Machine Learning Systems

Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time