Low Power LDPC Decoding by Reliable Voltage Down-Scaling

Low-Density Parity-Check (LDPC) decoder is among the power hungry building blocks of wireless communication systems. Voltage scaling down to Near-Threshold (NT) voltages substantially improves energy efficiency, in theory up 10x. However, tuning the voltage and clock frequency to the optimum error free operating point is challenging. This is mainly due to exacerbated sensitivity to Process, Voltage and Temperature (PVT) variations at reduced voltages. By definition, in many telecommunication standards, a Cyclic Redundancy Check (CRC) error detection is carried out after each forward error correction operation, e.g., LDPC decoding. Given channel information, successful CRC checking opens an opportunity for "safe" voltage down-scaling and optimum frequency tuning of LDPC decoder hardware. The strategy is explored on a Zynq System-on-Chip with CRC guiding the adaptive voltage scaling with microcontroller and LDPC decoder residing in different voltage islands. Around 40% power saving was achieved with negligible degradation in throughput.