Publications de Andreas Peter Burg

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We analyze the performance of quantized min-sum decoding of low-density parity-check codes under unreliable message storage. To this end, we introduce a simple bit-level error model and show that decoder symmetry is preserved under this model. Subsequently ...

Wireless sensors and actuators connected by the Internet-of-Things (IoT) are central to the design of advanced cyber-physical systems (CPSs). In such complex, heterogeneous systems, communication links must meet stringent requirements on throughput, latenc ...

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

The extension of multiple-input multiple-output (MIMO) sphere decoding from the narrowband case to wideband systems based on orthogonal frequency division multiplexing (OFDM) requires the computation of a QR decomposition for each of the data-carrying OFDM ...

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consum ...

In this work, we study the coded frame error rate (FER) of LoRa under additive white Gaussian noise (AWGN) and under carrier frequency offset (CFO). To this end, we use existing approximations for the bit error rate (BER) of the LoRa modulation under AWGN ...

Wireless radio consumes the highest power in many systems and must be activated wisely to save power especially in battery-powered systems. Hence, gathering insight into the spectrum activity is needed to control the wireless radio. In this work, classic f ...

The QR decomposition is an important, but often underestimated prerequisite for pseudo- or non-linear detection methods such as successive interference cancellation or sphere decoding for multiple-input multiple-output (MIMO) systems. The ability of concur ...

Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an avera ...

In-band full-duplex systems promise to further increase the throughput of wireless systems, by simultaneously transmitting and receiving on the same frequency band. However, concurrent transmission generates a strong self-interference signal at the receive ...

In this paper we investigate the impact of potential hardware misbehavior induced by reliability issues and scaled voltages in wireless body sensor network (WBSN) nodes. Our study reveals the inherent resilience of popular algorithms in cardiac monitoring ...

This paper deals with an energy-autonomous wireless sensing system with an indirect measurement of the light energy for ambient lighting sensing. The system can perform power measurements without battery or external power sources and generates time-domain ...

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

Scanning large bandwidths (spectrum sensing) pushes today’s analog hardware to its limits since periodic sampling at Nyquist rate with sufficient resolution is often prohibitively complex. In this paper, we consider a scenario where the signal to be acquir ...

This work presents an ADC-bascd receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols arc protected from the channel delay spread by the CP taps. A PAM- ...

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million o ...

The paper describes an algorithm and a corresponding VLSI architecture for the implementation of linear MMSE detection in packet-based MIMO-OFDM communication systems. The advantages of the presented receiver architecture are low latency, high-throughput, ...

Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process node ...

Andreas Peter Burg

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Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage

Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Interpolation-based QR decomposition in MIMO-OFDM systems

Impact of body biasing on the retention time of gain-cell memories

Coded LoRa Frame Error Rate Analysis

A Novel RF Spectrum Monitoring Architecture for an Ultra-Low-Power Wi-Fi Geopositioning System

VLSI implementation of a high-speed iterative sorted MMSE QR decomposition

VLSI implementation of MIMO detection using the sphere decoding algorithm

On the Implementation Complexity of Digital Full-Duplex Self-Interference Cancellation

Design of Energy Efficient and Dependable Health Monitoring Systems under Unreliable Nanometer Technologies

Intrinsically Self-powered, Battery-free, and Sensor-free Ambient Light Control System

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

2019 International Symposium on Low Power Electronics and Design

Random Sampling ADC for Sparse Spectrum Sensing

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI