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Andreas Peter Burg

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Publications associées (211)

Digital Predistortion of Power Amplifier Non-Linearities for Full-Duplex Transceivers

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Andrew Charles Mallory Austin

Non-linearities introduced by the power amplifier stage can significantly reduce the performance of self-interference cancellation in full-duplex transceivers. Accordingly, we propose a full-duplex system architecture that predistorts the digital baseband ...

Ieee2016

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Lorenz Flavio Schmid, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman, Thomas Christoph Müller

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Hardware Decoders for Polar Codes: An Overview

Andreas Peter Burg, Pascal Giard

Polar codes are an exciting new class of error correcting codes that achieve the symmetric capacity of memoryless channels. Many decoding algorithms were developed and implemented, addressing various application requirements: from error-correction performa ...

Ieee2016

Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Orion Afisiadis, Andrew Charles Mallory Austin

2016

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configur ...

Ieee2016

Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems

Andreas Peter Burg, Carl Christian Sten Dominic Senning, Georgios Karakonstantis

Energy in today's short-range wireless communication is mostly spent on the analog-and digital hardware rather than on radiated power. Hence, purely information-theoretic considerations fail to achieve the lowest energy per information bit and the optimiza ...

Springer Verlag2016

A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination

Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Adam Shmuel Teman, Reza Ghanaatian Jahromi

A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigo ...

Ieee2016

Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices

David Atienza Alonso, Pablo Garcia del Valle, Andreas Peter Burg, Loris Gérard Duch, Shrikanth Ganapathy

State-of-the-art wearable devices such as embedded biomedical monitoring systems apply voltage scaling to lower as much as possible their energy consumption and achieve longer battery lifetimes. While embedded memories often rely on Error Correction Codes ...

Ieee2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. hi contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

Ieee2016

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg, Adam Shmuel Teman

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

Approximate Computing With Unreliable Dynamic Memories

Andreas Peter Burg, Georgios Karakonstantis, Adam Shmuel Teman, Robert Giterman, Shrikanth Ganapathy

Embedded memories account for a large fraction of the overall silicon area and power consumption in modern SoC(s). While embedded memories are typically realized with SRAM, alternative solutions, such as embedded dynamic memories (eDRAM), can provide highe ...

2015

A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm

Andreas Peter Burg, Carl Christian Sten Dominic Senning, Nicholas Alexander Preyss

We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments ...

2015

Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications

Andreas Peter Burg, Georgios Karakonstantis, Adam Shmuel Teman, Shrikanth Ganapathy

Inherently error-resilient applications in areas such as signal processing, machine learning and data analytics provide opportunities for relaxing reliability requirements, and thereby reducing the overheads incurred by conventional error correction scheme ...

2015

Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Orion Afisiadis, Andrew Charles Mallory Austin

ACM Press2015

Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems

Andreas Peter Burg, Nicholas Alexander Preyss

A complete digital synchronization architecture for an IEEE 802.11ad compliant 60 GHz receiver is presented. The characteristics of mmWave systems require a holistic view on the problem of parameter estimation, such that not each parameter is dealt with on ...

2015

Effect of External Perturbation on Constellation Points in Beam-Space MIMO

Juan Ramon Mosig, Mohsen Yousefbeiki, Andreas Peter Burg

2015

An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar Codes

Andreas Peter Burg, Johannes Martin Wüthrich, Alexios Konstantinos Balatsoukas Stimming

2015

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

2015

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