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Andreas Peter Burg

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Related publications (211)

Fast-SSC-Flip Decoding of Polar Codes

Polar codes are widely considered as one of the most exciting recent discoveries in channel coding. For short to moderate block lengths, their error-correction performance under list decoding can outperform that of other modern error-correcting codes. Howe ...

2018

Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things

Andreas Peter Burg, Anupam Chattopadhyay

Wireless sensors and actuators connected by the Internet-of-Things (IoT) are central to the design of advanced cyber-physical systems (CPSs). In such complex, heterogeneous systems, communication links must meet stringent requirements on throughput, latenc ...

Ieee-Inst Electrical Electronics Engineers Inc2018

On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Pascal Giard

Polar codes are a recent family of error-correcting codes with a number of desirable characteristics. Their disruptive nature is illustrated by their rapid adoption in the 5 th-generation mobile-communication standard, where they are used to protect contro ...

IEEE2018

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

2018

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Adam Shmuel Teman, Reza Ghanaatian Jahromi, Thomas Christoph Müller

2018

An 800-MHz Mixed-V-T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

2018

Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming

2018

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Andreas Peter Burg, Lukas Kull, Thomas Toifl, Giovanni Cherubini

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

IEEE2018

Design and Implementation of a Neural Network Aided Self Interference Cancellation Scheme for Full-Duplex Radios

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yann Kurzo

In-band full-duplex systems are able to transmit and receive information simultaneously on the same frequency band. Due to the strong self-interference caused by the transmitter to its own receiver, the use of non-linear digital self interference cancellat ...

IEEE2018

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Nicholas Alexander Preyss, Andrea Bonetti, Adam Shmuel Teman

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman

Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Pascal Giard

Polar codes are a recently proposed family of provably capacity-achieving error-correction codes that received a lot of attention. While their theoretical properties render them interesting, their practicality compared to other types of codes has not been ...

Ieee2017

An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems

Pascal Junod, Andreas Peter Burg, Nicholas Alexander Preyss, Jeremy Hugues-Felix Constantin

Quantum key distribution (QKD) enables provably secure communication between two parties over an optical fiber that arguably withstands any form of attack. Besides the need for a suitable physical signalling scheme and the corresponding devices, QKD also r ...

Springer2017

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Andrea Bonetti, Thomas Christoph Müller, Pascal Giard

Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decoding algorithms, and they have an explici ...

2017

Blind detection of polar codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Pascal Giard

Polar codes were recently chosen to protect the control channel information in the next-generation mobile communication standard (5G) defined by the 3GPP. As a result, receivers will have to implement blind detection of polar coded frames in order to keep ...

2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Luca Benini, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Adam Shmuel Teman

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million o ...

Institute of Electrical and Electronics Engineers2017

A Multi-Gbps Unrolled Hardware List Decoder Systematic Polar Code

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Thomas Christoph Müller, Pascal Giard

Polar codes are a new class of block codes with an explicit construction that provably achieve the capacity of various communications channels, even with the low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more complex successive-c ...

2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

ACM2016

Spatial Multiplexing of QPSK Signals With a Single Radio: Antenna Design and Over-the-Air Experiments

Juan Ramon Mosig, Julien Perruisseau-Carrier, Mohsen Yousefbeiki, Andreas Peter Burg, Andrew Charles Mallory Austin

This paper describes the implementation and performance analysis of the first fully operational beam-space multiple-input multiple-output (MIMO) antenna for the spatial multiplexing of two QPSK streams. The antenna is composed of a planar three-port radiat ...

Institute of Electrical and Electronics Engineers2016

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