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Yusuf Leblebici

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Related publications (405)

Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Michail Zervas, Andreea Veronica Savu, Davide Sacchetto, Shenqi Xie

2011

Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications

Yusuf Leblebici, Davide Sacchetto, Izzet Yildiz

The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical-mechanical-po ...

Institute of Physics2011

Design trade-offs in ultra-low-power CMOS and STSCL digital systems

Yusuf Leblebici, Seyed Armin Tajalli

2011

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Yusuf Leblebici, Fengda Sun

Surface-tension-driven self-alignment (SA) is a promising technique for heterogeneous die-level stacking. Multiple dies can be manipulated in parallel at minimal cost. A defined amount of water present between the die and a carrier substrate is used to ali ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa

In this paper, we demonstrate the ability of the multi- spacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution and CMOS processing steps. We characterize sin ...

Institute of Electrical and Electronics Engineers2011

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

Paolo Ienne, Yusuf Leblebici, Stéphane Badel, Francesco Regazzoni

MOS Current Mode Logic (MCML) is one of the most promising logic style to counteract power analysis attacks. Unfortunately, the static power consumption of MCML standard cells is significantly higher compared to equivalent functions implemented using stati ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2011

Die-Level TSV Fabrication Platform for CMOS-MEMS Integration

Yusuf Leblebici, Michail Zervas, Yüksel Temiz, Carlotta Guiducci

This paper reports a new post-CMOS processing platform for die-level through-silicon-via (TSV) fabrication, based on wafer reconstitution from embedded dies, parylene deposition, stencil lithography, and bottom-up electroplating. The goal of this work is t ...

2011

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Davide Sacchetto

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fab ...

Elsevier2011

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properti ...

2011

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

Alexandre Schmid, Yusuf Leblebici, Vahid Majidzadeh Bafar

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to da ...

2011

3D Integration Technology for Lab-on-a-Chip Applications

Yusuf Leblebici, Samuel Kilchenmann, Yüksel Temiz, Carlotta Guiducci

A review is presented of advances and challenges in fully integrated systems for personalised medicine applications. One key issue for the commercialisation of such systems is the disposability of the assay-substrate at a low cost. This work adds a new dim ...

Institution of Engineering and Technology2011

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

Yusuf Leblebici, Seyed Armin Tajalli

In ultra-low-power (ULP) applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, re ...

Institute of Electrical and Electronics Engineers2011

VHDL-AMS Model of an Electrochemical Cell to Design VLSI Bio-Chips

Alain Vachoux, Yusuf Leblebici, Giovanni De Micheli, Sandro Carrara, Marialaura Beltrandi

This paper presents a new VHDL-AMS behavioral model of an electrochemical cell suitable for the design of VLSI bio-chips. Existing models are mainly equivalent circuit macromodels using electrical primitives, which hardly fit the actual behavior of biosens ...

2011

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto

Next generation logic switch devices are ex- pected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that ar ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff

Yusuf Leblebici, Stéphane Badel

In this paper, the impact of the wire grid size on the power-delay-area trade off of VLSI digital circuits with differential routing is analyzed. To this aim, the differential MOS current-mode logic (MCML) is adopted as reference logic style, and a complet ...

Elsevier2010

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Yusuf Leblebici, Seyed Armin Tajalli

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...

2010

Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Andreea Veronica Savu, Davide Sacchetto

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micro ...

2010

Very High Density Microelectrode Array with Monolithically Integrated Readout Circuits

Alexandre Schmid, Yusuf Leblebici, Neil Joye, Sedigheh Hashemi

This paper presents the hardware realization and modeling of high-density microelectrode arrays including both microelectronic readout amplifiers as well as three-dimensional microelectrodes forming a fully integrated CMOS compatible system enabling resear ...

2010

AM Modulation-based CMOS Readout Circuit for High-density Microelectrode Arrays

Alexandre Schmid, Yusuf Leblebici, Neil Joye

An innovative readout channel, based on analog amplitude modulation (AM) of the signals recorded by each electrode, is developed for high-density CMOS-based MEAs. This new readout method enables the design of a low-noise amplification stage while still rea ...

2010

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

Yusuf Leblebici, Seyed Armin Tajalli

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed techniq ...

DATE2010

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