Publications by Yusuf Leblebici

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The design of a high-density neural recording system targeting epilepsy monitoring is presented. Circuit challenges and techniques are discussed to optimize the amplifier topology and the included OTA. A new platform supporting active recording devices targeting wireless and high-resolution focus localization in epilepsy diagnosis is also proposed. The post-layout simulation results of an amplifier dedicated to this application are presented. The amplifier is designed in a UMC 0.18μm CMOS technology, has an

An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk) induced noise and to improve overall power efficiency. © 2015 JSAP.

Limited resources of embedded devices and increased real time constraints have raised interest to the binary description methods over the floating-point ones such as SIFT and SURF in computer vision applications. Although many software applications of the ...

This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...

A low-power 4-channel hybrid NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. The proposed system achieves 1 pJ/bit power efficiency, while communicating over an MDB channel with 45 dB loss at 3 GHz. The multi-tone (MT) nature of the proposed transceiver helps to control the intersymbol interference (ISI) and reduce the far-end crosstalk (FEXT), which results in a very energy-efficient implementation. The core size area is 80 x 60 um2

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate clocking for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC sta ...

We address the quantitative comparison of two basic connection schemes for on-chip communication, connection-oriented and connection-less, regarding their enforcement of a defined Quality-of-Service for the communication. For such comparison, we have built ...

One-Dimensional (1D) nanostructures have gained a considerable attention in the field of semiconductor technology for the past several decades. With the help of rapid development in the process technology, it becomes possible to scale these nanostructures ...

This brief analyzes the performance of the hardware-based tone mapping operators for compression of high dynamic range images. The bottlenecks of a tone mapping system are determined and a high-performance field programmable gate array (FPGA) implementatio ...

In this paper, we investigate different methods and approaches in order to improve the electrical characteristics of Pt/HfOx/TiN ReRAM devices. We discuss the improvement of the ReRAM electrical characteristics after the insertion of a Hf and Ti buffer lay ...

A new approach based on three-dimensional tip electrodes has been developed as a way to increase the electrical oupling between the neural cells and the individual sensors in a microelectrode array (MEA). With respect to standard planar electrodes, the ele ...

Multifrequency charge pumping analysis has been performed using a multiphonon-assisted charge trapping model in the view of analyzing the oxide region in energy and position that can be characterized using charge pumping (CP) characterization. Transient ph ...

Recently, studies on ReRAMs and their reliability have received increased attention. The reliability issue is due to the nature of oxygen vacancies behaviour under biasing conditions which necessitate further studies to achieve an in-depth understanding. I ...

This paper reports a micro electro-mechanical system (MEMS) based sensor array integrated with CMOS-based optical readout. The integrated architecture has several unique features. MEMS devices are passive and there are no electrical connections to the MEMS ...

Next generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant ...

This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local held and action potentials using an inverter-based capacitively coupled low-noise amplifier ...

Optical flow calculation algorithms are hard to implement on hardware level in real-time due to their complexity and high computational load. In this work, we present a novel hierarchical block matching based optical flow algorithm. The algorithm estimates ...

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fab ...

This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been ...

Yusuf Leblebici

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Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization

A 4x9 Gb/s 1 pJ/b NRZ/Multi-Tone Serial-Data Transceiver with Crosstalk Reduction Architecture for Multi-Drop Memory Interfaces in 40nm CMOS

A Bio-Inspired Reconfigurable Architecture for Local Binary Descriptors

A Low-Power Adaptive Bias/Clock Generator for Fine-Grained Voltage and Frequency Scaling in Multi-Core Systems

A 4×9 Gb/s 1 pJ/b Hybrid NRZ/Multi-Tone I/O with Crosstalk and ISI Reduction for Dense Interconnects

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Quantitative Modelling and Comparison of Communication Schemes to Guarantee Quality-of-Service in Networks-on-Chip

Top-Down Fabrication of Silicon Nanowires in Ultra-deep Trenches

Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

Effect of metal buffer layer and thermal annealing on HfOx-based ReRAMs

Three-Dimensional Silicon-based MEA with High Spatial Resolution

Precisely-timed synchronization among spiking neuron circuits on silicon neural networks - Analog implementation of integrate-and-fire neurons, depressing synapses, and STDP learning units

Modeling Stressed MOS Oxides Using a Multiphonon-Assisted Quantum Approach—Part II: Transient Effects

Evolution of oxygen vacancies under electrical characterization for HfOx-based ReRAMs

Design and characterization of micromachined sensor array integrated with CMOS based optical readout

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm2×fJ/conv-step Efficiency and 0.97 NEF

Block Matching Based Real-Time Optical Flow Hardware Implementation

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Case Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Cores