Publications de Yusuf Leblebici

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The damage inflicted to silicon nanowires (Si NWs) during the HF vapor etch release poses a challenge to the monolithic integration of Si NWs with higher-order structures, such as microelectromechanical systems (MEMS). This paper reports the development of ...

In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can ...

This work presents an ADC-bascd receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols arc protected from the channel delay spread by the CP taps. A PAM- ...

This paper reports a new post-CMOS processing platform for die-level through-silicon-via (TSV) fabrication, based on wafer reconstitution from embedded dies, parylene deposition, stencil lithography, and bottom-up electroplating. The goal of this work is t ...

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MS ...

This paper presents a monolithic approach for the integration of silicon nanowires (Si NWs) with microelectromechanical systems (MEMS). The process is demonstrated for the case of co-fabrication of Si NWs with a 10-μm-thick MEMS on the same silicon-on-insu ...

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data-rate 3D serial TSV links. A design space exploration is performed and trade-offs in terms of area, power and performance are presented. Circuit simulations of RC-extracted layouts in 40nm CMOS-technology reveals that 8:1 serialization efficiently balances

Self-heating effects became more prominent with the introduction of the modern devices like FD-SOI and low thermal conductivity materials such as SiO2. Consequently, the temperature rise of a device due to its self-heating is pronounced more as the gate le ...

This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach ha ...

In this paper, a novel SAR ADC architecture enabling very high speed operation is presented. Based on a hybrid capacitive DAC-threshold configuring scheme, the proposed architecture performs conversions in two-stages, similarly to pipelined ADCs. An additi ...

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devi ...

Omni-directional high resolution surveillance has a wide application range in defense and security fields. The GigaEye-1 system, with 44 single cameras and 22 FPGAs, is capable of recording omni-directional video in a 360º×100º FOV at 9.5 fps with a resolution over (17,000x5,000) pixels (85MP). Real-time video capturing capability is also verified at 30 fps for a resolution over (9,000x2,400) pixels (22MP). The important capacity of GigaEye-1 opens the door to various post-processing techniques in surveilla

Particle tracking detectors for High Energy Physics need a new readout technique to cope with the increase of the collision rate foreseen for the High Luminosity LHC upgrade. In particular, the selection of interesting physics events at the first trigger s ...

An omnidirectional sensor array system, for example a panoptic camera, comprising a plurality of sensors arranged on a support of predetermined shape to acquire data, wherein said sensors are directional and wherein each sensor is attached to a processing ...

Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In theory, the compressor trees contained within the multipliers could implement multi-input addition: however, they are not exposed to the programmer. To improve FPGA performance for these applications, this article introduces the Field Programmable Compressor Tree (FPCT

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...

The design of 3-dimensional integrated circuits requires new specialized tools, methods and flows. Whereas some tools are on the market and some design flows for standard ICs are extended to handle die stacking and through-silicon vias, much R&D has still ...

This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, ...

A multi-camera hemispherical very wide field of view imaging apparatus with omnidirectional illumination capability comprises a cylindrical body (4, 4.a, 4.b), a hemispherical mechanical frame (2) arranged on one end of the cylindrical body (4, 4.a, 4.b), ...

Wireless implantable devices capable of monitoring the electrical activity of the brain are becoming an important tool for understanding, and potentially treating, mental diseases such as epilepsy and depression. Compressive sensing (CS) is emerging as a p ...

Yusuf Leblebici

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Stencil lithography for bridging MEMS and NEMS

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Die-Level TSV Fabrication Platform for CMOS-MEMS Integration

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

Piezoresistivity characterization of silicon nanowires through monolithic MEMS

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Self-Heating Effects on the Thermal Noise of Deep Sub-Micron FD-SOI MOSFETs

Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC

Applications of Multi-Terminal Memristive Devices: A Review

A New Omni-Directional Multi-Camera System for High Resolution Surveillance

MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination

Omnidirectional sensor array system

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

Design Methods and Tools for 3D Integration

Analysis, Optimization, and Modeling of Analog Multi-Tone Serial Data Transceivers

Large field of view multi-camera endoscopic apparatus with omni-directional illumination

Structured Sampling and Recovery of iEEG Signals