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Jean-Michel Sallese

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Publications associées (155)

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult ...

Institute of Electrical and Electronics Engineers2016

Analysis of Substrate Currents Propagation in HVCMOS technology

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi ...

IEEE2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementar ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Active Guard Ring Characterization for Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

This paper shows SPICE simulation results of active guard ring structures which are typically employed in Smart Power ICs. Active guard rings act as barriers limiting the flow of minority carriers injected into the substrate toward sensitive circuits. The ...

Ieee2016

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Jean-Michel Sallese, Farzan Jazaeri, Ashkhen Yesayan

Nanowire (NW) semiconductors are interesting devices for being used as sensors. Such NWs are doped silicon channels with electrical contacts at both ends, which is a kind of the so-called junctionless (JL) device. However, in contrast with the state-of-the ...

Institute of Electrical and Electronics Engineers2016

Analog and RF Modeling of FDSOI UTBB MOSFET Using Leti-UTSOI Model

Christophe Lallement, Jean-Michel Sallese

Ultra-Thin Body and Box (UTBB) Fully-depleted Silicon-on-Insulator (FDSOI) MOSFETs exhibit very high transit frequency granting advantageous RF and low-power circuits design. This requires accurate models describing transistor behavior in all operating reg ...

IEEE2016

Spice Simulation of Passive Protection in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electr ...

Ieee2015

Modeling Parasitic Vertical PNP in HVCMOS

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach ...

IEEE2015

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

Jean-Michel Sallese, Farzan Jazaeri

This paper presents analytical expressions for channel noise, induced gate noise (IGN), and cross-correlation noise in a long-channel junctionless (JL) double-gate MOSFET. The analytical relationships, which have been derived from a coherent charge-based m ...

Ieee-Inst Electrical Electronics Engineers Inc2015

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are prop ...

Institute of Electrical and Electronics Engineers2015

Role of the gate in ballistic nanowire SOI MOSFETs

Christian Enz, Jean-Michel Sallese, Anurag Mangla

In this paper we report the results of Monte-Carlo simulations performed on double-gate ballistic MOSFETs with a geometry such that the gates overlap only a fraction of the channel. We present a qualitative analysis of the simulation results highlighting t ...

Elsevier2015

FOSS EKV 2.6 parameter extractor

Jean-Michel Sallese, Wladyslaw Grabinski, Anurag Mangla, Antonios Bazigos, Farzan Jazaeri, Maria-Anna Chalkiadaki

The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS techno ...

Ieee2015

Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

Classical substrate noise analysis considers the silicon resistivity of an integrated circuit only as doping dependent besides neglecting diffusion currents as well. In power circuits minority carriers are injected into the substrate and propagate by drift ...

Elsevier2015

Carrier Mobility Extraction Methodology in Junctionless and Inversion-Mode FETs

Jean-Michel Sallese, Farzan Jazaeri

In this paper, we propose a new method to extract the free carrier mobility in junctionless (JL) double-gate FETs biased in accumulation. We show that, in addition to assuming a well-defined field-dependent mobility law, using the well-known Y-function is ...

Institute of Electrical and Electronics Engineers2015

Impact of enhanced contact doping on minority carriers diffusion currents

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

Minority carriers diffusion currents are particularly important in parasitic substrate couplings of Smart Power ICs. In CMOS technologies the P-substrate potential is imposed by P+ contacts and N-wells by N+ highly doped implantations. The doping concentra ...

IEEE2014

Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

Jean-Michel Sallese, Mihai Adrian Ionescu, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1 x 10(19) cm(-3) n-type channel doping, 5-20 nm Si nanowire wi ...

Pergamon-Elsevier Science Ltd2014

Trans-Capacitance Modeling in Junctionless Gate-All-Around Nanowire FETs

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

In this letter, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme re ...

Elsevier2014

Optimization Strategy of Numerical Simulations Applied to EPFL Substrate Model

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit ...

Ieee2014

Submicrometer Organic Thin-Film Transistors: Technology Assessment Through Noise Margin Analysis of Inverters

Christian Enz, Jean-Michel Sallese, Rolando Ferrini, Frédéric Zanella, Nenad Marjanovic, Franz Xaver Pengg

In this paper, we propose a methodology to evaluate the potential of submicrometer organic thin-film transistors (OTFTs) with nanoimprinted gate and self-aligned source and drain contacts. In the first step, the dedicated static model we previously reporte ...

Institute of Electrical and Electronics Engineers2014

Spice Simulation of Substrate Minority Carriers Propagation with Equivalent Electrical Circuit

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

This paper presents an equivalent electrical circuit for one dimensional substrate minority carriers spice simulation. The electrical circuit parameters are extracted from substrate meshing applying the finite difference method. This model is derived from ...

Ieee2014

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