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Jean-Michel Sallese

Cette personne a quitté l’EPFL

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Publications associées (150)

Page 4 sur 8

Nonhysteretic Condition in Negative Capacitance Junctionless FETs

Jean-Michel Sallese, Farzan Jazaeri, Amin Rassekh

This article analyzes the design space stability of negative capacitance double-gate junctionless field-effect transistors (NCDG JLFETs). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

Jean-Michel Sallese, Farzan Jazaeri

This paper presents analytical expressions for channel noise, induced gate noise (IGN), and cross-correlation noise in a long-channel junctionless (JL) double-gate MOSFET. The analytical relationships, which have been derived from a coherent charge-based m ...

Ieee-Inst Electrical Electronics Engineers Inc2015

Mobility Extraction Assessment in GAA Si NW JL FETs with Cross-Section Down to 5 nm

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first ...

IEEE2013

Explicit drain current model of junctionless double-gate field-effect transistors

Jean-Michel Sallese, Ashkhen Yesayan

This paper presents an explicit drain current model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor. Analytical relationships for the channel charge densities and for the drain current are derived as explicit functions of ...

Pergamon-Elsevier Science Ltd2013

Carrier Mobility Extraction Methodology in Junctionless and Inversion-Mode FETs

Jean-Michel Sallese, Farzan Jazaeri

In this paper, we propose a new method to extract the free carrier mobility in junctionless (JL) double-gate FETs biased in accumulation. We show that, in addition to assuming a well-defined field-dependent mobility law, using the well-known Y-function is ...

Institute of Electrical and Electronics Engineers2015

FCC-ee: The Lepton Collider: Future Circular Collider Conceptual Design Report Volume 2

Yi Zhang, Jan Steggemann, Hua Zhang, Elena Graverini, Pierluigi Bruzzone, Jean-Michel Sallese, Luca Rossi, Mikhail Chapochnikov, Mathias Oleg Knecht, Doohyun Kim, Yu Bai, Fabio Avino, Xavier Buffat, Tatiana Pieloni, Andrea Wulzer, Michael Schenk, Marco Drewes, José Luis Abelleira Fernández, Mithlesh Kumar, Alexandra Sarabando de Carvalho, Leonid Rivkin, Alban Sublet, Alexej Grudiev, Roberto Contino, Francesco Cerutti, Sondre Vik Furuseth, Vincenzo D'Auria, Luca Vecchi, Javier Barranco Garcia, Claudia Tambasco, Sandra Aumon, Agnieszka Chmielinska, Georgi Gorine, Bernhard Auchmann, Léon Van Riesen-Haupt, Lotta Maria Mether

In response to the 2013 Update of the European Strategy for Particle Physics, the Future Circular Collider (FCC) study was launched, as an international collaboration hosted by CERN. This study covers a highest-luminosity high-energy lepton collider (FCC-e ...

2019

Noise Modeling in Lateral Nonuniform MOSFET

Christian Enz, Jean-Michel Sallese, Ananda Sankar Roy

In this paper, we present an analytical noise modeling methodology for lateral nonuniform MOSFET. We demonstrate that the noise properties of lateral nonuniform MOSFETs are considerably different from the prediction obtained with the conventional Klaassen- ...

2007

Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology

Jean-Michel Sallese, Didier Bouvet, Lucian Barbut

This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the r ...

IEEE2011

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut

This paper aims to model asymmetric operation in double gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concep ...

Institute of Electrical and Electronics Engineers2014

SOI Pixel Based on a Floating Body Partially Depleted MOSFET in a Delta-Sigma Loop

Maher Kayal, Jean-Michel Sallese

Standard techniques used for measuring the photocurrent of an SOI phototransistor have failed due to two main reasons: the first being the low signal-to-noise ratio and the second being the slow transient. In this paper, the partially depleted silicon on i ...

Institute of Electrical and Electronics Engineers2009

Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

Jean-Michel Sallese, Farzan Jazaeri, Amin Rassekh

In this article, an analytical predictive model of interface charge traps in symmetric, long-channel double-gate, junctionless transistors (JLTs) is proposed based on a charge-based model. Interface charge traps arising from exposure to chemicals, high-ene ...

2019

The Equivalent-Thickness Concept for Doped Symmetric DG MOSFETs

Jean-Michel Sallese

In this paper, we propose to derive an analytical model for the doped symmetric double-gate (DG) MOSFET that is valid in all regions of operation. We show that doping the silicon channel can be converted in an equivalent silicon thickness and threshold vol ...

2010

Towards circuit design using VeSFETs

Maher Kayal, Jean-Michel Sallese, François Krummenacher, Marc Pastre, Lucian Barbut

This paper explores the potential of VeFETs for mixed-signal circuits. A new physics-based compact DC model of the VeSFET operated in subthreshold region is presented and used to derive 1st-order sensitivities of the device threshold voltage to process var ...

2011

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

Jean-Michel Sallese, Alessandro Mapelli

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic ...

Institute of Physics2016

Corrosion Behavior of Heat-Treated Fe-Based Shape Memory Alloys

Jean-Michel Sallese, Stefano Mischler, Anna Neus Igual Muñoz, Pranav Vivek Kulkarni

The influence of various heat treatments on the corrosion behavior of a novel iron-based shape memory alloy (Fe-SMA), Fe-17Mn-6Si-10Cr-4Ni-1(V,C), used as prestressing elements in civil engineering was examined through electrochemical corrosion methods. SM ...

2025

Optimization Strategy of Numerical Simulations Applied to EPFL Substrate Model

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit ...

Ieee2014

Geometry influence on the Hall effect devices performance

Maher Kayal, Jean-Michel Sallese, Maria-Alexandra Paun

The influence of the geometry, via the ratio L/W of the Hall cells and the geometrical correction factor G on several figures of merit regarding Hall sensors is analyzed, namely the sensitivity, Hall Voltage and power dissipated within the device. Experime ...

2010

FCC-hh: The Hadron Collider: Future Circular Collider Conceptual Design Report Volume 3

Yi Zhang, Jan Steggemann, Hua Zhang, Elena Graverini, Pierluigi Bruzzone, Jean-Michel Sallese, Luca Rossi, Mikhail Chapochnikov, Mathias Oleg Knecht, Doohyun Kim, Yu Bai, Fabio Avino, Xavier Buffat, Tatiana Pieloni, Andrea Wulzer, Michael Schenk, Marco Drewes, José Luis Abelleira Fernández, Mithlesh Kumar, Alexandra Sarabando de Carvalho, Leonid Rivkin, Vincenzo D'Auria, Alban Sublet, Alexej Grudiev, Roberto Contino, Francesco Cerutti, Sondre Vik Furuseth, Javier Barranco Garcia, Claudia Tambasco, Sandra Aumon, Agnieszka Chmielinska, Bernhard Auchmann, Lotta Maria Mether, Léon Van Riesen-Haupt

In response to the 2013 Update of the European Strategy for Particle Physics (EPPSU), the Future Circular Collider (FCC) study was launched as a world-wide international collaboration hosted by CERN. The FCC study covered an energy-frontier hadron collider ...

2019

High-rate, high-resolution single photon X-ray imaging: Medipix4, a large 4-side buttable pixel readout chip with high granularity and spectroscopic capabilities

Jean-Michel Sallese, Adil Koukab, Viros Sriskaran

The Medipix4 chip is the latest member in the Medipix/Timepix family of hybrid pixel detector chips aimed at high -rate spectroscopic X-ray imaging using high -Z materials. It can be tiled on all 4 sides making it ideal for constructing large -area detecto ...

Iop Publishing Ltd2024

Simulation of CMOS APS Operation and Crosstalk in SPICE With Generalized Devices

Jean-Michel Sallese, Chiara Rossi

We present SPICE simulations of a CMOS APS pixel element consisting of the optical sensor with the sensing circuit. The photodiode is simulated at the physics level by means of the so-called Generalized Devices, without any predefined compact model. Conver ...

2020