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Jean-Michel Sallese

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Publications associées (155)

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

This paper aims to model asymmetric operation in double gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concep ...

Institute of Electrical and Electronics Engineers2014

Evaluation of characteristic parameters for high performance hall cells

Maher Kayal, Jean-Michel Sallese, Maria-Alexandra Paun

The current work focuses on presenting specific Hall cells with high performance, and their corresponding parameters. The design, integration, measurements and model development for their performance assessment are necessary stages considered in the genera ...

Elsevier Sci Ltd2014

Modeling the Channel Charge and Potential in Quasi-Ballistic Nanoscale Double-Gate MOSFETs

Christian Enz, Jean-Michel Sallese, Anurag Mangla

In this paper, we present an analytical semiempirical model of the profile of the channel charge and potential in quasi-ballistic double-gate (DG) MOSFETs. The charge model is based on the premise of separating the charge density in the quasi-ballistic cha ...

Ieee-Inst Electrical Electronics Engineers Inc2014

Generalized Charge Based Model of Double Gate Junctionless FETs Including Inversion

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

In this brief, we have developed a charge-based model for the symmetric double gate junctionless FET that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a for ...

Institute of Electrical and Electronics Engineers2014

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowi ...

Institute of Electrical and Electronics Engineers2014

Measurement and Compact Modeling of 1/f Noise in HV-MOSFETs

Matthias Bucher, François Krummenacher, Jean-Michel Sallese, Antonios Bazigos

This paper investigates 1/f noise behavior under low and high drain biases of high-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) (HV-MOSFETs). A dedicated setup is presented which allows measuring low-frequency (LF) noise of lateral ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Jean-Michel Sallese, Adil Koukab, Lucian Barbut, Farzan Jazaeri

In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along ...

Elsevier2013

Transient Off-Current in Junctionless FETs

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless fieldeffect transistors. This effect might be attributed to a process involving generati ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drai ...

2013

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier l ...

2013

Temperature considerations on Hall Effect sensors current-related sensitivity behaviour

Maher Kayal, Jean-Michel Sallese, Maria-Alexandra Paun

The present paper focuses on evaluating the temperature effects on Hall Effect sensors sensitivity behavior. To this purpose, an analysis of the factors affecting the sensors current-related sensitivity is performed, consisting of several pertinent conside ...

Springer US2013

Trans-Capacitance Modeling in Junctionless Symmetric Double Gate MOSFETs

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

We have developed a closed-form solution for trans-capacitances in long-channel Junctionless Double Gate MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with Technology Computer Aided Design simulations. Acco ...

Institute of Electrical and Electronics Engineers2013

Design and modeling of self-aligned nano-imprinted sub-micrometer pentacene-based organic thin-film transistors

Christian Enz, Jean-Michel Sallese, Randoald Müller, Rolando Ferrini, Frédéric Zanella, Nenad Marjanovic

Sub-micrometer channel length (0.5 mu m) organic thin-film transistors (OTFTs) are demonstrated using a process flow combining nano-imprint lithography (NIL) and self-alignment (SA). A dedicated test structure was designed and samples were fabricated on 4- ...

Elsevier2013

A Common Core Model for Junctionless Nanowires and Symmetric Double Gate FETs

Christophe Lallement, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

In this brief, we evidence the link between planar and cylindrical junctionless FETs from the electrostatics point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for junctionless nanowires can be mapped on th ...

Institute of Electrical and Electronics Engineers2013

System-Level Design Considerations for Carbon Nanotube Electromechanical Resonators

Maher Kayal, Jean-Michel Sallese, Marc Pastre, Christian Kauth

Despite an evermore complete plethora of complex domain-specific semiempirical models, no succinct recipe for large-scale carbon nanotube electromechanical systems design has been formulated. To combine the benefits of these highly sensitive miniaturized m ...

Hindawi Publishing Corporation2013

Mobility Extraction Assessment in GAA Si NW JL FETs with Cross-Section Down to 5 nm

Jean-Michel Sallese, Mihai Adrian Ionescu, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first ...

IEEE2013

Explicit drain current model of junctionless double-gate field-effect transistors

Jean-Michel Sallese, Ashkhen Yesayan

This paper presents an explicit drain current model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor. Analytical relationships for the channel charge densities and for the drain current are derived as explicit functions of ...

Pergamon-Elsevier Science Ltd2013

A Circuit Model for CMOS Hall Cells Performance Evaluation including Temperature Effects

Maher Kayal, Jean-Michel Sallese, Maria-Alexandra Paun

In order to provide the information on their Hall voltage, sensitivity, and drift with temperature, a new simpler lumped circuit model for the evaluation of various Hall cells has been developed. In this sense, the finite element model proposed by the auth ...

Hindawi Publishing Corporation2013

Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonst ...

2013

On performance scaling and speed of junctionless transistors

Jean-Michel Sallese, Adil Koukab

A prospective study of the junctionless transistors (JLTs) scaling performances based both on TCAD and analytical evaluations of the intrinsic delay after considering on/off voltage constraints is proposed. The tradeoffs between speed and switching power p ...

Pergamon-Elsevier Science Ltd2013

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