Publications by Yusuf Leblebici

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A partially parallel low density parity check (LDPC) decoder compliant with the IEEE 802.3an standard for 10GBASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up ...

The computational complexity of disparity estimation algorithms and the need of large size and bandwidth for the external and internal memory make the real-time processing of disparity estimation challenging, especially for High Resolution (HR) images. Thi ...

This paper presents an approach for analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition ...

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold ...

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data co ...

The presence of a direct band gap1-4 and an ultrathin form factor5 has caused a considerable interest in two-dimensional (2D) semiconductors from the transition metal dichalcogenides (TMD) family with molybdenum disulfide (MoS2) being the most studied repr ...

An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redund ...

3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data ...

Yusuf Leblebici

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A 5.35 mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS

Dynamically adaptive real-time disparity estimation hardware using iterative refinement

Fault-Tolerant Logic Gates with Neuromorphic CMOS Circuits

Predictable System Interconnects Through an Accurate Early Wire Characterization

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

MoS2 Transistors Operating at Gigahertz Frequencies

Adaptive Vgs: A Novel Technique for Controlling Power and Delay of Logic Gates in Sub-VT Regime

A 3D Stacked Multi-Core Processor Platform with Improved Testability

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics

Spherical Panorama Construction using Multi Sensor Registration Priors and Its Real-time Hardware

MoS2 Transistors Operating at Gigahertz Frequencies

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Toward a single-electron image processor for edge detection based on the inner retina model

A Bio-Inspired Image Processor for Edge Detection with Single-Electron Circuits

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

CONAN - A Design Exploration Framework for Reliable Nano-Electronics Architectures

A Bio-Inspired Image Processor for Edge Detection with Single-Electron Circuits