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Yusuf Leblebici

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Related publications (405)

Analysis and Optimization of MPSoC Reliability

Yusuf Leblebici, Giovanni De Micheli, Ayse Kivilcim Coskun

Advancements in technology enable integration of multiple devices on a single core, resulting in increased on chip power and temperature densities. Higher temperatures, in turn, present a significant challenge for reliability. In this work we propose a com ...

2006

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

An assessment of the fault-tolerance properties of single-ended and differential signaling is shown in the context of a high defect density environment, using a robust error-absorbing circuit architecture. A software tool based on Monte-Carlo simulations i ...

IEEE2006

Charge-Based CMOS Realization of Unconventional Functions

Alexandre Schmid, Yusuf Leblebici

2006

Low-Power Adaptive Bias/Clock Generator Using 0.18um CMOS Technology for Multi-Core Continuous Voltage and Frequency Scaling

Yusuf Leblebici, Zeynep Toprak Deniz

This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...

2005

CONAN - A Design Exploration Framework for Reliable Nano-Electronics Architectures

Alexandre Schmid, Yusuf Leblebici, Mihai Adrian Ionescu

2005

Design of Low-Power DPA-Resistant Cryptographic Functional Units

Paolo Ienne, Yusuf Leblebici, Ajay Kumar Verma, Zeynep Toprak Deniz

2005

Nanowire for Room Temperature Operated Hybrid CMOS-‘NANO’ Integrated Circuits

Michel Declercq, Serge Ecoffey, Alexandre Schmid, Yusuf Leblebici, Vincent Pott, Mihai Adrian Ionescu, Marco Mazza

2005

A Low-Power Adaptive Bias/Clock Generator for Fine-Grained Voltage and Frequency Scaling in Multi-Core Systems

Yusuf Leblebici, Zeynep Toprak Deniz

2005

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...

2005

Precisely-timed synchronization among spiking neuron circuits on silicon neural networks - Analog implementation of integrate-and-fire neurons, depressing synapses, and STDP learning units

Alexandre Schmid, Yusuf Leblebici

2005

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

IEEE2005

New Logic Family Based on Hybrid MOSFET-Polysilicon Nano-Wires

Didier Bouvet, Michel Declercq, Serge Ecoffey, Alexandre Schmid, Yusuf Leblebici, Vincent Pott, Mihai Adrian Ionescu, Marco Mazza

2005

Low-Power Current Mode Logic for Improved DPA-Resistance in Embedded Systems

Yusuf Leblebici, Zeynep Toprak Deniz

In this work, MOS Current Mode Logic (MCML) is analyzed for low power, low noise, mixed signal applications demanding high security such as embedded cryptographic processors and smart cards. We emphasize the possible extension of MCML gate usage for low sp ...

2005

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying ...

2005

Fabrication of polysilicon gated-nanowires and their application for pA precision current measurements

Didier Bouvet, Michel Declercq, Serge Ecoffey, Yusuf Leblebici, Vincent Pott, Mihai Adrian Ionescu

2005

Towards a Unified Top-Down Design Flow for Fully-Differential Logic Blocks with Improved Speed and Noise Immunity

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noiseimmune designs consisting of differential logic blocks. The differential building blocks are based on the currentmode logic (CML), which offers true differentiali ...

2005

A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance Analysis

Alexandre Schmid, Yusuf Leblebici, Vineet Abhishek, Milos Stanisavljevic

This paper presents a new approach for monitoring and estimating device reliability of nanometer-scale devices prior to fabrication. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. A complete tool for ...

IFIP2005

Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

Paul Victor Georges Muller, Yusuf Leblebici

In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data ...

2005

Semi-Automated Design of a MOS Current Mode Logic Standard Cell Library from Generic Components

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

This paper describes the design and semi-automated generation of a MOS current-mode logic standard cell library. A set of generic components implementing a wide range of combinational and sequential functions is proposed. The layout of the generic componen ...

2005

Fault-Tolerant Logic Gates with Neuromorphic CMOS Circuits

Alexandre Schmid, Yusuf Leblebici, Neil Joye

2005

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