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Yusuf Leblebici

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Publications associées (405)

Fostering the Reuse and Collaborative Development of Models in the AMS SoC Design Process

Alain Vachoux, Yusuf Leblebici, Torsten Mähne

Systems-on-Chips (SoCs) integrate more and more heterogeneous components: analog/RF/digital circuits, sensors, actuators, software. For the design of these systems very different description formalisms, or Models of Computation (MoCs), and tools are used f ...

IEEE2007

Solid-state electronics special issue foreword

Yusuf Leblebici, Mihai Adrian Ionescu

2007

Case Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Cores

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic, Maria Gabrani

This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been ...

2007

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

Eric Vittoz, Yusuf Leblebici, Omer Can Akgun

In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can ...

2007

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies

Paolo Ienne, Yusuf Leblebici, Stéphane Badel, Zeynep Toprak Deniz, Francesco Regazzoni

2007

Fault Tolerance of Feed-Forward Artificial Neural Network Architectures Targeting Nano-Scale Implementations

Alexandre Schmid, Yusuf Leblebici, Ayfer Özgür Aydin, Mehmet Vural

2007

A Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technology

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a power-efficient and low-voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption ...

IEEE Service Center2007

A 90nm CMOS Cryptographic Core with Improved Fault- Tolerance in Presence of Massive Defect Density

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

2007

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This paper presents an approach for analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition ...

IEEE2006

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers very high noise immunity due to the differential ope ...

2006

Via-Programmable Structured ASIC Fabric Based on MCML Cells: Design-Flow and Implementation

Yusuf Leblebici, Stéphane Badel

This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers high speed operation, very high noise immunity, as w ...

2006

Via-Programmable Expanded Universal Logic Gate in MCML for Structured ASIC Applications: Circuit Design

Yusuf Leblebici, Stéphane Badel, Ilhan Hatirnaz

This paper presents a via-programmable expanded universal logic gate in MOS current-mode logic which can implement any 3-input Boolean function, and a significant subset of 4-input and 5-input functions. The universal logic gate is programmed with the firs ...

2006

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are d ...

IEEE2006

A Simulation Methodology for Reliability Analysis in Multi-Core SoCs

Yusuf Leblebici, Giovanni De Micheli, Ayse Kivilcim Coskun

Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to higher temperature and adverse effects on reliability. In this paper, we introduce ...

ACM Press2006

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

Eric Vittoz, Yusuf Leblebici, Zeynep Toprak Deniz

2006

A Predictable Communication Scheme for Embedded Multiprocessor Systems

Paolo Ienne, Yusuf Leblebici, Mehmet Harmanci

Networks-on-Chip are emerging as a widely accepted alternative for the traditional bus architectures. However, their applicability by the system designers is far away from being intuitive due to their lack of predictability. This communication predictabili ...

2006

Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

Yusuf Leblebici, Omer Can Akgun

In this paper the advantages of using Differential Cascode Voltage Switch Pass Gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and Energy-Delay-Product ( ...

2006

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Yusuf Leblebici

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Fostering the Reuse and Collaborative Development of Models in the AMS SoC Design Process

Solid-state electronics special issue foreword

Case Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Cores

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies

Fault Tolerance of Feed-Forward Artificial Neural Network Architectures Targeting Nano-Scale Implementations

A Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technology

A 90nm CMOS Cryptographic Core with Improved Fault- Tolerance in Presence of Massive Defect Density

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

Via-Programmable Structured ASIC Fabric Based on MCML Cells: Design-Flow and Implementation

Via-Programmable Expanded Universal Logic Gate in MCML for Structured ASIC Applications: Circuit Design

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

A Simulation Methodology for Reliability Analysis in Multi-Core SoCs

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

A Predictable Communication Scheme for Embedded Multiprocessor Systems

Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

Configurable on-line global energy optimization in multi-core embedded systems using principles of analog computation

Via-programmable Structured ASIC Fabric Based on MCML Cells (poster)

How much faster can we go ? : A technology outlook (invited presentation)