Publications by Yusuf Leblebici

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In this paper, we analyze the 6T SRAM cell failures caused by temperature and supply voltage variations, and we explore the design of robust SRAM cells for high temperature operation. This integral SRAM reliability study is performed using 180nm SOI CMOS p ...

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The propo ...

Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime the circuit delay, and hence, the leakage energy consumption depend on the supply voltage exponentially. By re ...

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40nm CMOS node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations an ...

Introducing a single silicon nanowire with a known orientation and dimensions to a specific layout location constitutes a major challenge. The challenge becomes even more formidable, if one chooses to realize the task in a monolithic fashion with an extrem ...

Systems-on-Chips (SoCs) integrate more and more heterogeneous components: analog/RF/digital circuits, sensors, actuators, software. For the design of these systems very different description formalisms, or Models of Computation (MoCs), and tools are used f ...

Complex yet compact nanoscale mechanisms have largely been absent due to the rather limited availability of components and integration techniques. Especially missing have been efficient interconnects with adjustable characteristics. To address this issue, ...

We review our work towards achieving competitive performance (classification accuracies) for on chip machine learning (ML) of large scale artificial neural networks (ANN) using Non-Volatile Memory (NVM) based synapses, despite the inherent random and deter ...

Panoptic is a custom spherical light field camera used as a polydioptric system where imagers are distributed over a hemispherical surface, each having its own vision of the surroundings and a distinct focal plane. The spherical light field camera records ...

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type charact ...

A multiphonon-assisted model included in a Poisson-Schroedinger solver has been applied for the calculation of the capture/emission trapping rates of Si/SiO2 interface defects and their dependence with respect to the trap energy and depth in the oxide. The ...

A CMOS imager is presented which has the abil- ity to perform localized compressive sensing on-chip. In-pixel convolutions of the sensed image with measurement matrices are computed in real time, and a proposed programmable two- dimensional scrambling tech ...

The modelling and simulation capabilities of SystemC-AMS concerning conservative continuous time systems involving the interaction of several physical domains and with digital control components are currently limited. Bond graphs unify the description of m ...

This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...

High quality CMOS image sensors are of great importance for LoC - Lab-on-Chip devices based on optical measurements. The main target in these devices is to minimize the cost and area while achieving a good resolution. The performance parameters of image se ...

An innovative readout channel, based on analog amplitude modulation (AM) of the signals recorded by each electrode, is developed for high-density CMOS-based MEAs. This new readout method enables the design of a low-noise amplification stage while still rea ...

The paper discusses the recent achievements in the development of chips with integrated sensing of biomolecules. In particular, it focuses on integrated sensing electrodes on silicon and presents innovative solutions for the enhanced robustness of the elec ...

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for u ...

This paper presents the hardware realization and modeling of high-density microelectrode arrays including both microelectronic readout amplifiers as well as three-dimensional microelectrodes forming a fully integrated CMOS compatible system enabling resear ...

Yusuf Leblebici

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Design of High-Temperature SRAM for Reliable Operation Beyond 250 C

A Hybrid CDAC-Threshold Configuring SAR ADC in 28nm FDSOI CMOS

A Current Sensing Completion Detection Method for Asynchronous Pipelines Operating In the Sub-threshold Regime

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

A Deep Etching Mechanism for Trench-Bridging Silicon Nanowires

Fostering the Reuse and Collaborative Development of Models in the AMS SoC Design Process

Observation of coupled mechanical resonance modes within suspended 3D nanowire arrays

Large-scale neural networks implemented with nonvolatile memory as the synaptic weight element: comparative performance analysis (accuracy, speed, and power)

Image Blending in a High Frame Rate FPGA-based Multi-Camera System

Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited

AC analysis of defect cross sections using non-radiative MPA quantum model

A (256x256) Pixel 76.7mW CMOS Imager/ Compressor Based on Real-Time In-Pixel Compressive Sensing

Development of a Bond Graph Based Model of Computation for SystemC-AMS

Low-Power Adaptive Bias/Clock Generator Using 0.18um CMOS Technology for Multi-Core Continuous Voltage and Frequency Scaling

Characterization of Standard CMOS Compatible Photodiodes and Pixels for Lab-on-Chip Devices

AM Modulation-based CMOS Readout Circuit for High-density Microelectrode Arrays

Integrating Bio-sensing Functions on CMOS Chips

Early Wire Characterization for Predictable Network-on-Chip Global Interconnects

Very High Density Microelectrode Array with Monolithically Integrated Readout Circuits