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Pierre-Emmanuel Julien Marc Gaillardon

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Publications associées (119)

Emerging Technology Based Design of Primitives for Hardware Security

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon

Hardware security concerns such as IP piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this paper, emerging technologies are investigated by leveraging their uniq ...

Assoc Computing Machinery2016

Majority-Inverter Graph: A New Paradigm for Logic Optimization

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

In this paper, we propose a paradigm shift in representing and optimizing logic by using only majority (MAJ) and inversion (INV) functions as basic operations. We represent logic functions by Majority-Inverter Graph (MIG): a directed acyclic graph c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Optimizing Majority-Inverter Graphs with Functional Hashing

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken

A Majority-Inverter Graph (MIG) is a recently introduced logic representation form whose algebraic and Boolean properties allow for efficient logic optimization. In particular, when considering logic depth reduction, MIG algorithms obtained signific ...

IEEE2016

Exploiting Inherent Characteristic of Reversible Circuits for Faster Combinational Equivalence Checking

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

Reversible circuits implement invertible logic functions. They are of great interest to cryptography, coding theory, interconnect design, computer graphics, quantum computing, and many other fields. As for conventional circuits, checking the combinational ...

Ieee2016

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jury Sandrini, Pierre-Emmanuel Julien Marc Gaillardon, Tugba Demirci, Maxime Victor Thammasack, Marios Barlas

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

Institute of Electrical and Electronics Engineers2016

Polarity control in WSe2 double-gate transistors

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Giovanni Vincenzo Resta

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-d ...

Nature Research2016

Majority-based Synthesis for Nanotechnologies

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

We study the logic synthesis of emerging nanotechnologies whose elementary devices abstraction is a majority voter. We argue that synthesis tools, natively supporting the majority logic abstraction, are the technology enablers. This is because they allow d ...

Ieee2016

LUT Mapping and Optimization for Majority-Inverter Graphs

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Winston Jason Haaswijk, Mathias Soeken

A Majority-Inverter Graph (MIG) is a directed acyclic graph in which every vertex represents a three-input majority operation and edges may be complemented to indicate operand inversion. MIGs have algebraic and Boolean properties that enable efficie ...

2016

A Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Giovanni De Micheli, Hassan Ghasemzadeh Mohammadi, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

This paper deals with the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of fau ...

2016

An MIG-based Compiler for Programmable Logic-in-Memory Architectures

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on r ...

Ieee2016

Inversion optimization in majority-inverter graphs

Giovanni De Micheli, Luca Gaetano Amarù, Odysseas Zografos, Pierre-Emmanuel Julien Marc Gaillardon, Eleonora Testa, Mathias Soeken

Many emerging nanotechnologies realize majority gates as primitive building blocks and they benefit from a majority-based synthesis. Recently, Majority-Inverter Graphs (MIGs) have been introduced to abstract these new technologies. We present optimi ...

Ieee2016

Notes on Majority Boolean Algebra

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Anupam Chattopadhyay, Mathias Soeken

A Majority-Inverter Graph (MIG) is a homogeneous logic network, where each node represents the majority function. Recently, a logic optimization package based on the MIG data-structure, with 3-input majority node (M3) has been proposed [2], [30]. It is dem ...

IEEE2016

Resistive Switching Element and Use Thereof

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Tugba Demirci

A bipolar resistive switching device including an electrically conductive bottom electrode, a stack of transition metal oxides layers, a number of transition metal oxide layers being equal or greater than 2, the stack including: at least one MOx layer, at ...

2016

Pattern-based fpga logic block and clustering algorithm

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 t ...

2016

High-performance low-power near-vt resistive memory-based fpga

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and ...

2016

Method for speeding up boolean satisfiability

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic ...

2016

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion

Giovanni De Micheli, Gain Kim, Luca Gaetano Amarù, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

Nowadays, Field Programmable Gate Arrays (FPGA) exploit Look-Up Tables (LUTs) to generate logic functions. A K-input LUT can implement any Boolean functions with K inputs. Thanks to this flexibility, LUTs remained concep ...

2015

A Fast Pruning Technique for Low-Power Inexact Circuit Design

Giovanni De Micheli, Jaime Joven Murillo, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Johan Broc

Inexact Circuits are circuits in which the accuracy of the output can be traded for cost savings (energy, area and/or delay). In the context of advanced technology scaling and power density increase, inexact circuits appear to be very promising as ...

IEEE2015

Exploiting Circuit Duality to Speed Up SAT

Giovanni De Micheli, Maciej Jerzy Ciesielski, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

In this paper, we establish a non-trivial duality between tautology and contradiction check to speed up circuit SAT. Tautology check determines if a logic circuit is true in every possible interpretation. Analogously, contradiction check dete ...

IEEE2015

A Study on Buffer Distribution for RRAM-based FPGA Routing Structures

Giovanni De Micheli, Somayyeh Rahimian Omam, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

Compared to Application-Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) provide reconfigurablity at the cost of lower performance and higher power consumption. Exploiting a large number of programmable switche ...

IEEE2015

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