Publications de Farzan Jazaeri

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In this article, an analytical predictive model of interface charge traps in symmetric, long-channel double-gate, junctionless transistors (JLTs) is proposed based on a charge-based model. Interface charge traps arising from exposure to chemicals, high-ene ...

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier ...

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, ...

This paper highlights some of the challenges faced for the modeling of MOSFET devices for operation at cryogenic temperature (CT). A special focus is given on the modeling of the threshold voltage V-T and the subthreshold swing SS. The significant increase ...

This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a ...

In this paper, a comprehensive charge-based predictive model of interface and oxide trapped charges in undoped symmetric long-channel double-gate MOSFETs is developed. The model involves essentially no fitting parameters, but first-principle calculations o ...

This paper presents a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field-effect transistors. The intrinsic model is physics-based and does not introduce any empirical parameter. The central concept is ...

Using the Y-function method, this paper experimentally investigates the effects of total ionizing dose up to 1 Grad on the channel mobility of a commercial 28-nm bulk CMOS process. ...

This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of nMOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual nMOSFETs of various siz ...

This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative ca ...

Gate-lag induced trapping effects due to donor-like surface traps located in the access regions between the electrodes of AlGaN/GaN HEMTs are investigated through TCAD transient simulations. The effects of variation in trap energy level and temperature on ...

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowi ...

In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method fo ...

The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS techno ...

This paper uses the simplified charge-based EKV MOSFET model for studying the effects of total ionizing dose (TID) on analog parameters and figures-of-merit (FoMs) of 28nm bulk MOSFETs. These effects are demonstrated to be fully captured by the five key pa ...

This paper demonstrates and experimentally reports the highest ever performance boosting in strained silicon-nanowire homojunction TFETs with negative capacitance, provided by matched PZT capacitors. Outstanding enhancements of I on , g m , and overdrive a ...

We investigate the technological con-strains and design limitations of ultrathin body junctionless dou- ble gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of ...

In this article, we propose an explicit and analytic charge-based model for estimating short-channel effects (SCEs) in GaN high-electron-mobility transistor (HEMT) devices. The proposed model is derived from the physical charge-based core of the ecole Poly ...

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drai ...

We have developed a closed-form solution for trans-capacitances in long-channel Junctionless Double Gate MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with Technology Computer Aided Design simulations. Acco ...

Farzan Jazaeri

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Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

Ultrathin Junctionless Nanowire FET Model, Including 2-D Quantum Confinements

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Cryo-CMOS Compact Modeling

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

Charge-Based Modeling of Radiation Damage in Symmetric Double-Gate MOSFETs

Charge-Based EPFL HEMT Model

Mobility Degradation of 28-nm Bulk MOSFETs Irradiated to Ultrahigh Total Ionizing Doses

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Negative Capacitance Field Effect Transistors; Capacitance Matching and non-Hysteretic Operation

Study of Donor-like Surface Trap Emission in GaN HEMTs

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs

FOSS EKV 2.6 parameter extractor

Total Ionizing Dose Effects on Analog Performance of 28 nm Bulk MOSFETs

Negative capacitance tunnel F£Ts: Experimental demonstration of outstanding simultaneous boosting of on-current, transconductance, overdrive, and swing

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

Modeling of Short-Channel Effects in GaN HEMTs

Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

Trans-Capacitance Modeling in Junctionless Symmetric Double Gate MOSFETs