Publications de Vincent Pott | EPFL Graph Search

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This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI ...

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always be ...

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measur ...

In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Omega-MOSFET). The Omega-MOSFETs are fabricated on low-doped (8x10(14)cm(-3)) bulk silicon by bulk silicon isotropic etching and sacrificial oxidation. A specific abrupt impact ionization and hysteresis of I-D(V-DS) are observed at high drain voltage (V-DS > 11V) on transistors that have short channel effects (L=0.9-10um). This is explained by the

This work reports on memory applications of punch-through impact ionization single-transistor latch (PIMOS), showing abrupt current switching (3-10mV/dec.) as well as hysteresis in both ID(VDS) and ID(VGS). A capacitor-less 1PIMOS - 1 MOSFET DRAM memory is ...

A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid- state MOS transistor and a suspended metal membrane in a unique metal-over- gate architecture, is proposed. A unified physical analytical model (weak, moderate and strong inversions) is developed and used to investigate main electrostatic characteristics in order to provide first-order design criteria for low-voltage operation and high-performance. It is demonstrated that the use of a thin gate oxide (

This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching ...

This paper discusses three categories of small slope electronic switches: the Tunnel FET the IMOS and the NEM-FET which are expected to bring added value compared to CMOS by presenting an abrupt subthreshold slope, smaller than the physical limit, 60mV/decade, of the solid-state MOS transistor at room temperature. Recent results and future promises are reported.

The recently proposed PIMOS transistor can offer, by appropriate operation, non-hysteretic abrupt off-on transitions due to impact ionization if the action of its parasitic bipolar transistor is minimized. This work proposes non-hysteretic abrupt inverter ...

In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200MPa to 2GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied [Omega]- and tri-gate structures to obtain abrupt switching (3-10 mV/decade) combined with a hysteresis in the ID(VDS ...

This paper presents a process for the co-fabrication of self-aligned NMOS and single electron transistors made by gated polysilicon wires. The realization of SET–MOS hybrid architectures is also reported. The proposed process exploits an original low energ ...

Vincent Pott

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Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

Gate-all-around silicon nanowires for hybrid single electron transistor/CMOS applications

The high-mobility bended n-channel silicon nanowire transistor

Abrupt current switching due to impact ionization effects in Omega-MOSFET on low doped bulk silicon

DRAM Based on Hysteresis in Impact Ionization Single-Transistor-Latch

Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG- MOSFET) with a metal-over-gate architecture

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

Small slope micro/nano-electronic switches

Non-hysteretic punchthrough impact ionization MOS (PIMOS) transistor: Application to abrupt inverter and NDR circuits

Co-integration of gate-all-around MOSFETs and local silicon-on insulator optical waveguides on bulk silicon for GHz on-chip optical signaling

Low temperature investigation of electrical conduction in polysilicon: simulation and experiment

Nanowire for Room Temperature Operated Hybrid CMOS-‘NANO’ Integrated Circuits

New Logic Family Based on Hybrid MOSFET-Polysilicon Nano-Wires

Coulomb blockade in gate-all-around silicon nanowire MOSFETs

Bended gate-all-around nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

Hybrid Nanowire-MOS circuit architectures: from basic physics to digital and analog applications

Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

Gate-all-around MOSFETs: true fabrication and characteristics

A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires

Low temperature single electron characteristics in gate-all-around MOSFET