Publications de Yusuf Leblebici

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Elliptic curve cryptosystems (ECCs) are utilised as an alternative to traditional public-key cryptosystems, and are more suitable for resource-limited environments because of smaller parameter size. In this study, the authors carry out a thorough investiga ...

An assessment of the fault-tolerance properties of single-ended and differential signaling is shown in the context of a high defect density environment, using a robust error-absorbing circuit architecture. A software tool based on Monte-Carlo simulations i ...

This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined to operate in the subthreshold regime. The flow is applicable on gate-level netlists, where back-annotated toggle informa ...

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The scheme utilizes an identical pseudo-random sequence for every image column, therefore reducing in-pixel hardware complexity and allowing measurement ...

The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical-mechanical-po ...

A novel compressive sampling scheme suitable for highly scalable hardware implementation is presented. The prototype design is implemented in a 0.18um standard CMOS technology and utilizes compressed acquisition to achieve high frame rates and maintain low power consumption. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measu

Compressive Sampling (CS) offers bandwidth, power and memory size reduction compared to conventional (Nyquist) sampling. However, very few Integrated Circuit (IC) designs based on CS exist due to the missing link between the well-established CS theory on o ...

The precise evaluation of the reliability of logic circuits has a significant importance in highly-defective and future nanotechnologies. It allows efficient comparison of fault-tolerance techniques, and enables designs improvement with respect to their re ...

In this paper, we demonstrate the ability of the multi- spacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution and CMOS processing steps. We characterize sin ...

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacito ...

Next generation logic switch devices are ex- pected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that ar ...

The importance of developing predictive modeling tools has considerably increased with the diffusion of nanoscale technologies, in which strained layers and heterojunctions determine the materials modeling complexity. A self--consistent Poisson--Schroedinger solver based on a full-band k.p method within the envelope-function approximation has been developed and validated on large test structures, studying the oxide capacitance for various gate stacks. Among the effects governing the electrostatics of the de

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

A new plenoptic sensor inspired from the visual system of flying insects is introduced. This sensor is referred to as the Panoptic camera. This system has two distinguished features. First it is an omnidirectional camera capable of recording light information around it. Second it is a polydioptric system where each CMOS facet has a distinct focal plane; hence the full system is multiple aperture camera. An FPGA based solution is proposed for real time application deployment. The omnidirectional vision recon

A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of c ...

This work proposes a new approach to characterize the mechanical properties of nanowires based on a combination of nanomechanical measurements and models. Silicon nanowires with a critical dimension of 90 nm and a length of 8 mu m obtained through a monoli ...

Capacitor mismatch in high resolution Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) causes non-linearity effects that reduce the Spurious-Free Dynamic Range (SFDR). This paper presents a novel dynamic element matching (DEM) te ...

This paper presents a low power successive approximation register (SAR) ADC and its front-end automatic gain control (AGC) amplifier designed in 65nm CMOS technology. Digitally controlled variable gain amplifier (VGA) in AGC loop is used to maximize the dy ...

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of being monolithically integrated with CMOS chips, Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting t

Yusuf Leblebici

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Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

High-Level Energy Estimation in the Sub-VT Domain: Simulation and Measurement of a Cardiac Event Detector

Column-Separated Compressive Sampling Scheme for Low Power CMOS Image Sensors

Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications

High Frame-Rate Low-Power Compressive Sampling CMOS Image Sensor Architecture

Compressive Image Acquisition in Modern CMOS IC Design

Output Probability Density Functions of Logic Circuits: Modeling and Fault-Tolerance Evaluation

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

Modeling study of capacitance and gate current in strained High–K Metal gate technology: impact of Si/SiO2/HK interfacial layer and band structure model

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Hardware Implementation of an Omnidirectional Camera with Real-time 3D Imaging Capability

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

A new characterization approach to study the mechanical behavior of silicon nanowires

A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCs

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)