Publications de Yusuf Leblebici

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This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random fail ...

Machine Learning (ML) is an attractive application of Non-Volatile Memory (NVM) arrays [1,2]. However, achieving speedup over GPUs will require minimal neuron circuit sharing and thus highly area-efficient peripheral circuitry, so that ML reads and writes ...

A new plenoptic sensor inspired from the visual system of flying insects is introduced. This sensor is referred to as the Panoptic camera. This system has two distinguished features. First, it is an omnidirectional camera capable of recording light information around it. Second, it is a polydioptric system where each CMOS facet has a distinct focal plane; hence the full system is a multiple aperture camera. An FPGA based solution is proposed for real time application deployment. The omnidirectional vision r

Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their org ...

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18um standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Spec ...

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangem ...

Three-point bending tests were performed on double-anchored, < 110 > silicon nanowire samples in the vacuum chamber of a scanning electron microscope ( SEM) via a micromanipulator equipped with a piezoresistive force sensor. Nanowires with widths of 35nm a ...

Despite the huge research effort to improve the performance of the complementary metal oxide semiconductor (CMOS) image sensors, charge-coupled devices (CCDs) still dominate the cell biology-related conventional fluorescence microscopic imaging market wher ...

This paper presents an experimental study on different microelectrode fabrication techniques, with particular focus on the robustness of the surface insulation towards typical working conditions required in lab-on-a-chip applications. Pt microelectrodes wi ...

This paper presents a novel approach to acquire multichannel wireless intracranial neural data based on a compressive sensing scheme. The designed circuits are extremely compact and low-power which confirms the relevance of the proposed approach for multic ...

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

Inspiration from light field imaging concepts has led to the construction of multi-aperture imaging systems. Using multiple cameras as individual apertures is a topic of high relevance in the light field imaging domain. The need for wide field-of-view (FOV ...

We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of ...

A sixth-order low-pass

g_m

-C filter with a very wide tuning range (

f_c

= 100 Hz to 10 MHz) is presented. The wide tuning range has been achieved without using switchable components or programmable building blocks. A single stage folded-cascode transcon ...

In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data ...

This article presents a neural recording amplifier suitable for large-scale integration with multi-electrode arrays (MEAs) in very low-power microelectronic cortical implants. The proposed amplifier is the most energy-efficient structure reported to date, ...

We present a 16-channel seizure detection system-on-chip (SoC) with 0.92μW/channel power dissipation in a total area of 1.1mm² including a closed-loop neural stimulator. A set of four features are extracted from the spatially filtered neural data to achiev ...

A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-t ...

In this paper a novel approach to optimize digital integrated circuits yield with regards to speed and area/power for aggressive scaling technologies is presented. The technique is intended to reduce the effects of intra-die variations using redundancy app ...

A power and area effcient hardware encoding system tailored for wireless implantable applications is presented. Constant medical monitoring allowed by implantable devices is the most relevant alternative to current bulky monitoring systems, which, in case ...

Yusuf Leblebici

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Design and Realization of a Fault-Tolerant 90nm Cryptographic Engine Capable of Performing under Massive Defect Density

Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays

A Real-time Multi-camera System with Omnidirectional Image Reconstruction Capability

Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique

Power-Efficient CMOS Image Acquisition System based on Compressive Sampling

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

Determination of the Elastic Behavior of Silicon Nanowires within a Scanning Electron Microscope

Empowering Low-Cost CMOS Cameras by Image Processing to Reach Comparable Results with Costly CCDs

A Comparative Study on Fabrication Techniques for On-Chip Microelectrodes

Compressive Multichannel Cortical Signal Recording

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Hemispherical Multiple Camera System for High Resolution Omni-Directional Light Field Imaging

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

A Micropower Neural Recording Amplifier with Improved Noise Efficiency Factor

A 16-Channel 1.1mm2 Implantable Seizure Control SoC with Sub-μW/Channel Consumption and Closed-Loop Stimulation in 0.18μm CMOS

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

Selective Redundancy-Based Design Techniques for the Minimization of Local Delay Variations

An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems