Publications de Yusuf Leblebici

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This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180 nm CMOS technology chips. The proposed integration method enables low- cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory sy ...

Feature detection and description constitute important steps of many computer vision applications such as object detection and panorama stitching. Since those steps are computationally heavy, they might occupy significant portion of the full operation. Alt ...

A three-dimensional tip electrode array technology for in- vitro electrophysiological experiments is presented. Based on simulation results obtained with a finite element model of the neuron-electrode interface, it has been shown that the electrical coupli ...

A surface potential-based model for embedded flash memory cells has been developed with the purpose of providing a comprehensive physical understanding of the device operation suitable for performance optimization in memory circuit design. The device equations account for charge balance effects on the isolated floating gate node and parasitic couplings between the terminals of the memory cell. The compact model supports DC, AC and transient analyses, including program/erase bias scalability, drain disturb a

This paper presents a single-chip trinocular disparity estimation processor, capable of computing in real-time up to 2048×1080 resolution depth maps at 32fps with up to 256-pixel disparity range using two/three CMOS camera sensors. The most important featu ...

Networks-on-Chip are emerging as a widely accepted alternative for the traditional bus architectures. However, their applicability by the system designers is far away from being intuitive due to their lack of predictability. This communication predictabili ...

Super-resolution reconstruction is a method for reconstructing higher resolution images from a set of low resolution observations. The sub-pixel differences among different observations of the same scene allow to create higher resolution images with better ...

This paper presents a serial link transceiver (TRX) architecture that enables high-speed data transmission over a lossy backplane channel without the presence of equalization circuits. The proposed architecture employs multi-tone signaling to reduce inter- ...

An innovative readout channel, based on analog amplitude modulation of the signals recorded by each sensing site, is developed for high-density CMOS-based microelectrode arrays. A single amplification stage simultaneously records the neural activity acquir ...

A novel CMOS image sensor is proposed to overcome the analog design limitations in Active Pixel Sensors - APS and large area overcome in Digital Pixel Sensors - DPS for use in bio-medical applications. The design includes a pixel level event generation mec ...

This paper proposes a hardware-oriented trinocular adaptive window size disparity estimation (T-AWDE) algorithm and the first real-time trinocular disparity estimation (DE) hardware that targets high-resolution images with high-quality disparity results. T ...

This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...

This paper reports on the memory and memristive effects of Schottky barrier field effect transistors (SBFET) with gate-all-around (GAA) configuration and Si nanowire (SiNW) channel. Similar behavior has also been investigated for SBFETs with poly-Si nanowire (poly-SiNW) channel in back-gate configuration. The memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid CMOS co-fabrication with a CMOS-compatible process. We show that 2 different re

This article presents a power-efficient and low-voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption ...

The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correc ...

Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to higher temperature and adverse effects on reliability. In this paper, we introduce ...

The current trend in constructing high-end computing systems consists of parallelizing large numbers of processors. A similar trend is observed in digital imaging where multiple camera inputs are utilized to obtain multiple images of a scene and thus enhan ...

Neuromorphic computing takes inspiration from the brain to build highly parallel, energy- and area-efficient architectures. Recently, hardware realizations of neurons and synapses using memristive devices were proposed and applied for the task of correlati ...

Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing system. Memory systems typically apply dual in-line memory modules (DIMMs) because of their high capacity and low cost. However, the multi-drop bus (MDB) interface between these units and the controller is challenging for bandwidth and power reasons. Multi-tone signaling has promising characte

Implantable systems are nowadays being used to interface the human brain with external devices, in order to understand and potentially treat neurological disorders. The most predominant design constraints are the system’s area and power. In this paper, we ...

Yusuf Leblebici

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Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

Hardware Implementation of a Smart Camera with Keypoint Detection and Description

Three-dimensional Tip Electrode Array Technology for High Resolution Neuro-Electronic System used in Electrophysiological Experiments in-vitro

Surface potential compact model for embedded flash devices oriented to IC memory design

A Single-chip 2048x1080 Resolution 32fps 380mW Trinocular Disparity Estimation Processor in 28nm CMOS Technology

A Predictable Communication Scheme for Embedded Multiprocessor Systems

Hardware implementation of real-time multiple frame super-resolution

Architectural Modeling of a Multi-Tone/Single-Sideband Serial Link Transceiver for Lossy Wireline Data Links

Extracellular recording system based on amplitude modulation for CMOS microelectrode arrays

An event-detection high dynamic range CMOS image sensor

Trinocular Adaptive Window Size Disparity Estimation Algorithm and Its Real-Time Hardware

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Memristive Devices Fabricated with Silicon Nanowire Schottky Barrier Transistors

A Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technology

A Stochastic Perturbative Approach to Design a Defect-Aware Thresholder in the Sense Amplifier of Crossbar Memories

A Simulation Methodology for Reliability Analysis in Multi-Core SoCs

Design and Implementation of Multi-camera Systems Distributed over a Spherical Geometry

Neuromorphic Architecture with 1M Memristive Synapses for Detection of Weakly Correlated Inputs

10.3 A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces in 40nm CMOS

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants