Publications de Yusuf Leblebici

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We report here on a new insight for bio-sensing based on the memristive effect of functionalized Schottky-barrier memristive silicon nanowire in dry environment. The device concept is discussed. Electrical measurements confirm the bio-detection by the narr ...

Polarimetric imaging techniques demonstrate enhanced capabilities in advanced object detection tasks with their capability to discriminate man-made objects from natural background surfaces. While spectral signatures carry information only about material pr ...

Accurate electrical models are needed to support the design of modern microelectrode arrays. The point-contact model is presented thoroughly, and an area-contact model is analytically derived in order to model the electrical characteristics of the cell-ele ...

A novel hardware implementation of an omnidirectional image sensor is presented which is capable of acquiring and processing 3D image sequences in real time. The system consists of a hemispherical arrangement of a large number of CMOS imagers, connecting t ...

Complementary MOS device electrical performances are considerably affected by the degradation of the oxide lay- ers and Si/SiO2 interfaces. A general expression for electrically stressed MOS impedance has been derived and applied within the nonradiative mu ...

This work describes a NRZ receiver data-path fabricated in 14nm bulk FinFET technology and characterized in an 850nm VCSEL based optical link up to 64Gb/s. It achieves 1.42pJ/bit energy efficiency while recovering PRBS-7 data (BER< 10-12) modulated by a VC ...

A point-contact model is presented, and an areacontact model has been analytically derived in order to model the electrical characteristic of the cell-electrode interface of high-density neuron cultures. The area-contact model is presented as a model more ...

This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operati ...

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved pow ...

Yusuf Leblebici

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Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth

Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs

New Insight on Bio-sensing by Nano-fabricated Memristors

Target Detection with Deep Learning in Polarimetric Imaging

Solid-state electronics special issue foreword

Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays

Charge-Based CMOS Realization of Unconventional Functions

Hardware Implementation of an Omnidirectional Camera with Real-Time 3D Imaging Capability

Modeling Stressed MOS Oxides Using a Multiphonon-Assisted Quantum Approach—Part I: Impedance Analysis

A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET

Pin-shape assessment for interlayer-cooled chip stacks with periodic boundary condition modeling

Design Space Exploration for Field Programmable Compressor Trees

On the Fault-Tolerance of a Clustered Single-Electron Neural Network for Differential Enhancement

An Electrical Model of the Cell-Electrode Interface for High-density Microelectrode Arrays

Fault-tolerant architectures for nanoelectronic circuits employing simple feed-forward neural networks without learning

Compact Electro-Thermal Model for Thermal Cross-Talk Analysis in PCM Arrays

Fabrication of polysilicon gated-nanowires and their application for pA precision current measurements

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

Improving the power-delay performance in subthreshold source-coupled logic circuits

Design trade-offs in ultra-low-power CMOS and STSCL digital systems