Publications de Yusuf Leblebici

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Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer ...

This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency ...

The recent development of high quality free viewpoint synthesis algorithms and their implementations allows to realize glasses-free 3D perception. Although many algorithms are developed on this domain, the real-time hardware realization of a free viewpoint ...

This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channe ...

An event-driven analogue-to-digital converter (ADC) architecture is proposed. The proposed architecture has less sensitivity to amplifier and DAC nonlinearity, and reduces the swing and dynamic common-mode range requirement of the operational transconducta ...

Yusuf Leblebici

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Implementation of early vision model for edge extraction with single-electron devices

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces

Fault Tolerance of Feed-Forward Artificial Neural Network Architectures Targeting Nano-Scale Implementations

A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation

A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons

Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays

A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS

A Low-power 490 MPixels/s Hardware Accelerator for Pyramidal Decomposition of Images

Toward a bio-inspired image processor for edge extraction with single-electron devices

Designing secure systems: Manufacturing, circuits and architectures

Single-Electron Circuit for Inhibitory Spiking Neural Network with Fault-Tolerant Architecture

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology

Real-Time Free Viewpoint Synthesis Using Three-Camera Disparity Estimation Hardware

A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Via-programmable Structured ASIC Fabric Based on MCML Cells (poster)

Low-distortion switched-capacitor event-driven analogue to-digital converter

3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling