Publications de Didier Bouvet | EPFL Graph Search

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We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless fieldeffect transistors. This effect might be attributed to a process involving generati ...

Wafer bonding is an established technology for the manufacturing of silicon-on-insulator (SOI) substrates, microelectromechanical systems (MEMS) and microfluidic devices. Low temperature direct bonding techniques can be of particular interest for the fabri ...

We present the fabrication and high frequency characterization of a capacitive nanoelectromechanical system (NEMS) switch using a dense array of horizontally aligned single-wall carbon nanotubes (CNTs). The nanotubes are directly grown onto metal layers wi ...

In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200MPa to 2GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied [Omega]- and tri-gate structures to obtain abrupt switching (3-10 mV/decade) combined with a hysteresis in the ID(VDS ...

This paper presents a process for the co-fabrication of self-aligned NMOS and single electron transistors made by gated polysilicon wires. The realization of SET–MOS hybrid architectures is also reported. The proposed process exploits an original low energ ...

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier l ...

In this paper, we investigate the effect of different process parameters on oxidation-induced strain (OIS) into a doubly-clamped silicon nanowire FET to control and finally, enhance carrier mobility. Spacer technology together with sacrificial thermal oxid ...

The design, fabrication and characterization of Micro-electro-mechanical metal-air-insulator-semiconductor (MEM-MAIS) diode switch are originally reported. An abrupt switching from off-state to Fowler-Nordheim tunneling current in on-state is induced by th ...

This paper reports on the fabrication and electrical characterization of a novel pressure sensor based on a suspended-gate MOSFET (SG-MOSFET) using a new polyimide process. The device is composed of a SG-MOSFET built on a thin SOI membrane released by a ba ...

Didier Bouvet

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Co-integration of gate-all-around MOSFETs and local silicon-on insulator optical waveguides on bulk silicon for GHz on-chip optical signaling

Low temperature investigation of electrical conduction in polysilicon: simulation and experiment

Transient Off-Current in Junctionless FETs

Transient current technique for charged traps detection in silicon bonded interfaces

New Logic Family Based on Hybrid MOSFET-Polysilicon Nano-Wires

Capacitive nanoelectromechanical switch based on suspended carbon nanotube array

Coulomb blockade in gate-all-around silicon nanowire MOSFETs

Bended gate-all-around nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

Hybrid Nanowire-MOS circuit architectures: from basic physics to digital and analog applications

Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

Gate-all-around MOSFETs: true fabrication and characteristics

A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires

Low temperature single electron characteristics in gate-all-around MOSFET

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Investigation of oxidation-induced strain in a top-down Si nanowire platform

Electrical conduction in 10nm-thin polysilicon wires from 4K to 400K and their operation for hybrid memory

Micro-Electro-Mechanical Metal-Air-Insulator-Semiconductor Diode Switch

Polyimide sacrificial layer for SOI SG-MOSFET pressure sensor

High Quality Factor Copper Inductors Integrated in Deep Dry Etched Quartz Substrates

Local volume inversion and corner effects in triangular gate-all-around MOSFETs