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Farzan Jazaeri

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Related publications (81)

GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs

Christian Enz, Claudio Bruschini, Federico Faccio, Farzan Jazaeri, Chunmin Zhang, Alessandro Pezzotta

The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS tech ...

IEEE2016

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain ...

2016

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Jean-Michel Sallese, Farzan Jazaeri, Ashkhen Yesayan

Nanowire (NW) semiconductors are interesting devices for being used as sensors. Such NWs are doped silicon channels with electrical contacts at both ends, which is a kind of the so-called junctionless (JL) device. However, in contrast with the state-of-the ...

Institute of Electrical and Electronics Engineers2016

Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC

Christian Enz, Claudio Bruschini, Federico Faccio, Farzan Jazaeri, Chunmin Zhang, Alessandro Pezzotta

The Large Hadron Collider (LHC) running at CERN will soon be upgraded to increase its luminosity giving rise to radiations reaching the level of GigaRad Total Ionizing Dose (TID). This paper investigates the impact of such high radiation on transistors fab ...

IEEE2016

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

Jean-Michel Sallese, Farzan Jazaeri

This paper presents analytical expressions for channel noise, induced gate noise (IGN), and cross-correlation noise in a long-channel junctionless (JL) double-gate MOSFET. The analytical relationships, which have been derived from a coherent charge-based m ...

Ieee-Inst Electrical Electronics Engineers Inc2015

Modeling Junctionless Metal-Oxide-Semiconductor Field-Effect Transistor

Farzan Jazaeri

Metal-oxide semiconductor (MOS) field-effect transistor (FET) scaling is following the prediction of the Moore's law for the past 45 years, a key factor that enabled the IC industry to cope with the everlasting demand for higher performances. However, this ...

EPFL2015

FOSS EKV 2.6 parameter extractor

Jean-Michel Sallese, Wladyslaw Grabinski, Anurag Mangla, Antonios Bazigos, Farzan Jazaeri, Maria-Anna Chalkiadaki

The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS techno ...

Ieee2015

Carrier Mobility Extraction Methodology in Junctionless and Inversion-Mode FETs

Jean-Michel Sallese, Farzan Jazaeri

In this paper, we propose a new method to extract the free carrier mobility in junctionless (JL) double-gate FETs biased in accumulation. We show that, in addition to assuming a well-defined field-dependent mobility law, using the well-known Y-function is ...

Institute of Electrical and Electronics Engineers2015

Trans-Capacitance Modeling in Junctionless Gate-All-Around Nanowire FETs

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

In this letter, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme re ...

Elsevier2014

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

This paper aims to model asymmetric operation in double gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concep ...

Institute of Electrical and Electronics Engineers2014

Generalized Charge Based Model of Double Gate Junctionless FETs Including Inversion

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

In this brief, we have developed a charge-based model for the symmetric double gate junctionless FET that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a for ...

Institute of Electrical and Electronics Engineers2014

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowi ...

Institute of Electrical and Electronics Engineers2014

Transient Off-Current in Junctionless FETs

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless fieldeffect transistors. This effect might be attributed to a process involving generati ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Jean-Michel Sallese, Adil Koukab, Lucian Barbut, Farzan Jazaeri

In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along ...

Elsevier2013

Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drai ...

2013

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier l ...

2013

Trans-Capacitance Modeling in Junctionless Symmetric Double Gate MOSFETs

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

We have developed a closed-form solution for trans-capacitances in long-channel Junctionless Double Gate MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with Technology Computer Aided Design simulations. Acco ...

Institute of Electrical and Electronics Engineers2013

A Common Core Model for Junctionless Nanowires and Symmetric Double Gate FETs

Christophe Lallement, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

In this brief, we evidence the link between planar and cylindrical junctionless FETs from the electrostatics point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for junctionless nanowires can be mapped on th ...

Institute of Electrical and Electronics Engineers2013

Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

Didier Bouvet, Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonst ...

2013

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

Jean-Michel Sallese, Lucian Barbut, Farzan Jazaeri

We investigate the technological con-strains and design limitations of ultrathin body junctionless dou- ble gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of ...

Ieee-Inst Electrical Electronics Engineers Inc2013

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