Publications by Farzan Jazaeri

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This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer char ...

Nanowire (NW) semiconductors are interesting devices for being used as sensors. Such NWs are doped silicon channels with electrical contacts at both ends, which is a kind of the so-called junctionless (JL) device. However, in contrast with the state-of-the ...

This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC me ...

This paper presents an intensive overview of the characterization and modeling of advanced 28-nm hulk and FDSOI CMOS processes operating continuously from room down to deep cryogenic temperature. ...

In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along ...

This study presents the first in depth characterization of deep cryogenic electrical behavior of a commercial 16 nm CMOS FinFET technology. This technology is well suited for a broad range of applications, including quantum computing, quantum sensing, and ...

This paper investigates the effects of total ionizing dose up to 1 Grad on 28-nm bulk MOSFETs under different bias conditions during irradiation. The aim is to assess the potential use of this commercial bulk CMOS technology in the future high-luminosity L ...

In this paper, we propose an accurate method to extract the free carrier mobility in FETs. This derivation relies only on the drift-diffusion transport model without the need to predefine the gate-voltage-mobility dependence. This approach has been assesse ...

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier l ...

This paper demonstrates and experimentally reports the highest ever performance boosting in strained silicon-nanowire homojunction TFETs with negative capacitance, provided by matched PZT capacitors. Outstanding enhancements of Ion, gm, and overdrive are a ...

This letter reports a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures. Below a critical temperature, the derived limit saturates to a value that is independent of tempe ...

In this letter, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme re ...

This paper presents a generalized charge-based EKV MOSFET model that includes the effects of trapped charges in the bulk oxide and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge d ...

This paper introduces a simplified and design-oriented version of the EPFL HEMT model [1], focusing on the normalized transconductance-to-current characteristic (Gm/ID). Relying on these figures, insights into GaN HEMT modeling in relation to technology of ...

In this brief, we have developed a charge-based model for the symmetric double gate junctionless FET that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a for ...

Farzan Jazaeri

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Characterization and Modeling of 28-nm FDSOI CMOS Technology down to Cryogenic Temperatures

Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing

28-nm Bulk and FDSOI Cryogenic MOSFET (Invited Paper)

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing

Bias Dependence of Total Ionizing Dose Effects on 28-nm Bulk MOSFETs

Carrier Mobility Extraction in FETs

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Negative Capacitance Tunnel FETs: Experimental Demonstration of Outstanding Simultaneous Boosting of On-current, Transconductance, Overdrive, and Swing

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

Trans-Capacitance Modeling in Junctionless Gate-All-Around Nanowire FETs

Variability of Low Frequency Noise and mismatch in CORNER DOPED and standard CMOS technology

A Generalized EKV Charge-based MOSFET Model Including Oxide and Interface Traps

Simplified EPFL HEMT Model

Generalized Charge Based Model of Double Gate Junctionless FETs Including Inversion