Publications by Lucian Barbut | EPFL Graph Search

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This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonst ...

In this brief, we evidence the link between planar and cylindrical junctionless FETs from the electrostatics point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for junctionless nanowires can be mapped on th ...

This paper aims to model asymmetric operation in double gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concep ...

This paper explores the potential of VeFETs for mixed-signal circuits. A new physics-based compact DC model of the VeSFET operated in subthreshold region is presented and used to derive 1st-order sensitivities of the device threshold voltage to process var ...

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowi ...

We investigate the technological con-strains and design limitations of ultrathin body junctionless dou- ble gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of ...

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drai ...

We have developed a closed-form solution for trans-capacitances in long-channel Junctionless Double Gate MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with Technology Computer Aided Design simulations. Acco ...

In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along ...

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier l ...

In this letter, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme re ...

In this brief, we have developed a charge-based model for the symmetric double gate junctionless FET that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a for ...

Lucian Barbut

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Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

A Common Core Model for Junctionless Nanowires and Symmetric Double Gate FETs

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

Towards circuit design using VeSFETs

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

Trans-Capacitance Modeling in Junctionless Symmetric Double Gate MOSFETs

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Trans-Capacitance Modeling in Junctionless Gate-All-Around Nanowire FETs

Junctionless Transistors : Challenges and Opportunities in Fabrication and Characterization

Generalized Charge Based Model of Double Gate Junctionless FETs Including Inversion