Publication

Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

Jean-Michel Sallese, Farzan Jazaeri, Didier Bouvet, Lucian Barbut
2013
Conference Papers

Abstract

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonstrate up to six decades of Ion/Ioff ratio and a sub- threshold swing of 90 mV/decade relative to a slit width of approximately 10 nm.

Official source

https://infoscience.epfl.ch/entities/publication/caaf5b4b-89ec-48ae-9782-b8ef5517db06

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Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

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