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Seyed Armin Tajalli

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Related publications (48)

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A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

2007

A Digital Spectrum Shaping Signaling Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Interfaces

Yusuf Leblebici, Seyed Armin Tajalli, Gain Kim, Kiarash Gharibdoust

A transceiver (TRX) architecture employing spectrum shaping signaling scheme is proposed, which can significantly reduce inter-symbol interference (ISI) and crosstalk in multi-drop interfaces. The proposed TRX architecture relies on digital implementation ...

Ieee-Inst Electrical Electronics Engineers Inc2016

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...

2005

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying ...

2005

Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes

Mohammad Amin Shokrollahi, Seyed Armin Tajalli, Harm Cronie

In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a sparse signaling code, wherein a codeword is representable as a vector of a plu ...

2012

Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

Yusuf Leblebici, Seyed Armin Tajalli

The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS cir ...

2009

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

Yusuf Leblebici, Seyed Armin Tajalli

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. ...

2009

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Yusuf Leblebici, Seyed Armin Tajalli

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...

2010

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

Yusuf Leblebici, Seyed Armin Tajalli

A very low power mixed-signal design methodology based on subthreshold source-coupled circuits is presented, and a nano-Watt range analog-to-digital converter (ADC) circuit based on folding-interpolating topology is proposed as a complete design example. T ...

2010

Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

Yusuf Leblebici, Seyed Armin Tajalli

This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach ha ...

IEEE2008

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

IEEE2005

A 5.43-μW 0.8-V Subthreshold Current-Sensing Σ∆ Modulator for Low-Noise Sensor Interfaces

Yusuf Leblebici, Alexandre Schmid, Seyed Armin Tajalli, Nikola Katic

A micro-watt power subthreshold current modulator suitable for low-power and low-noise sensor interfaces is presented. The prototype design is based on Subthreshold Source Coupled Logic (STSCL) cells and implemented in a 0.18 μm standard CMOS technology. T ...

2014

Power and Area Efficient MOSFET-C Filter for Very Low Frequency Applications

Yusuf Leblebici, Seyed Armin Tajalli

New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power (ULP) biomedical systems. Ranging in value from few hundreds ...

Springer Verlag2012

Pico-Watt Source-Coupled Logic Circuits

Yusuf Leblebici, Seyed Armin Tajalli

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on d ...

2008

Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

Yusuf Leblebici, Seyed Armin Tajalli, Eric Vittoz

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can ...

2007

Wide tuning range linearity improved biquadratic transconductor-C filter

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a new technique for improving the linearity performance in biquadratic transconductor-C filters. This improvement has been achieved by applying some modifications to the filter topology which considerably relaxes the linearity require ...

2007

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

Yusuf Leblebici, Seyed Armin Tajalli

Power-frequency scaling in subthreshold source coupled logic (STSCL) systems has been studied and analyzed. It is shown that the operating frequency of such systems can be adjusted over about three decades with linearly proportional power dissipation. The ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. A source follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18um ...

2009

Design trade-offs in ultra-low-power CMOS and STSCL digital systems

Yusuf Leblebici, Seyed Armin Tajalli

2011

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Yusuf Leblebici, Andreas Peter Burg, Seyed Armin Tajalli, Firat Çelik, Ayça Akkaya

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

IEEE2019