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Seyed Armin Tajalli

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Publications associées (48)

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

Yusuf Leblebici, Seyed Armin Tajalli

A very low power mixed-signal design methodology based on subthreshold source-coupled circuits is presented, and a nano-Watt range analog-to-digital converter (ADC) circuit based on folding-interpolating topology is proposed as a complete design example. T ...

2010

Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

Seyed Armin Tajalli

The potentials of subthreshold metal-oxide-semiconductor (MOS) solid-state devices for implementing widely adjustable performance integrated circuits with very low power consumption have been investigated. The main concentration of this work is developing ...

EPFL2010

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Yusuf Leblebici, Seyed Armin Tajalli

A current-mode

\Delta\Sigma

analog-to-digital data converter (ADC) for biomedical readout front-end systems is being presented. The core of this circuit is a current-controlled ring oscillator (CCO) whose oscillation frequency is proportional to the inpu ...

2010

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

Yusuf Leblebici, Seyed Armin Tajalli

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. ...

2009

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design

Yusuf Leblebici, Seyed Armin Tajalli

The large subthreshold leakage current of static CMOS logic circuits designed in modern nanometer-scale technologies is one of the main barriers for implementing ultra-low power digital systems. Subthreshold source-coupled logic (STSCL) circuits are based ...

IEEE2009

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

Yusuf Leblebici, Seyed Armin Tajalli

A very wide tuning range ultra-low-power MOSFET-C filter is presented. The wide tuning range in this filter has been achieved without using any switchable components or programmable building blocks, and the cutoff frequency of the filter can be adjusted si ...

IEEE2009

Ultra-Low Power 32-bit Pipelined Adder Using Subthreshold Source-Coupled Logic with 5fJ/stage PDP

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a new approach for improving the power-delay performance of subthreshold source-couple logic (STSCL) circuits. Using a simple two-phase pipelining technique, it is possible to increase the activity rate of STSCL gates with negligible ...

2009

Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. A source follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18um ...

2009

Improving the power-delay performance in subthreshold source-coupled logic circuits

Yusuf Leblebici, Seyed Armin Tajalli

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved pow ...

Springer2009

A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power p ...

2009

Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

Yusuf Leblebici, Seyed Armin Tajalli

The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS cir ...

2009

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

Yusuf Leblebici, Thomas Liechti, Zeynep Toprak Deniz, Seyed Armin Tajalli, Omer Can Akgun

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...

IEEE2008

Pico-Watt Source-Coupled Logic Circuits

Yusuf Leblebici, Seyed Armin Tajalli

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on d ...

2008

Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications

Eric Vittoz, Yusuf Leblebici, Seyed Armin Tajalli

This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate cont ...

2008

Implementing Ultra-high-Value Floating Tunable CMOS Resistors

Yusuf Leblebici, Seyed Armin Tajalli

A compact high-value ﬂoating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 um CMOS technology to verify the proposed concept. This technique has been applied to design a reconﬁgurable sixt ...

2008

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

Yusuf Leblebici, Seyed Armin Tajalli, Mohammad Beikahmadi

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data co ...

NORCHIP2008

Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

Yusuf Leblebici, Seyed Armin Tajalli

This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach ha ...

IEEE2008

Wide tuning range linearity improved biquadratic transconductor-C filter

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a new technique for improving the linearity performance in biquadratic transconductor-C filters. This improvement has been achieved by applying some modifications to the filter topology which considerably relaxes the linearity require ...

2007

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

2007

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

Eric Vittoz, Yusuf Leblebici, Seyed Armin Tajalli

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold ...

2007

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