Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
A micro-watt power subthreshold current modulator suitable for low-power and low-noise sensor interfaces is presented. The prototype design is based on Subthreshold Source Coupled Logic (STSCL) cells and implemented in a 0.18 μm standard CMOS technology. The modulator operates with the supply voltage of 0.8 V which is significantly lower than the nominal supply of the technology node (1.8 V). It consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current-sensing resolution ranges from ENOB=7.1 bits at a 5 kHz bandwidth to ENOB=6.5 bits at a 20 kHz bandwidth. The obtained power-efficiency of 1.5 pJ per conversion outperforms any existing current-mode analog- to-digital converter (ADC) design and is comparable to conven- tional voltage-mode Continuous-Time (CT) Σ∆ modulators. The modulator generates very low levels of switching noise thanks to the continuous-time operation and subthreshold current-mode circuits that draw a constant subthreshold current from the voltage supply. The modulator is used as an interface for sensors with current-mode output in ultra low-power conditions and can also be used for power monitoring circuits.