Course

EE-530: Test of VLSI systems

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Lectures in this course (22)

Memory Evolution: From DRAM to SRAM

Covers the historical increase in memory cells per chip, the importance of memory in modern IC architectures, the dramatic increase in test time, and various memory faults.

Test of VLSI Systems

Covers test techniques for digital VLSI systems, including fault modeling and design for testability.

Testing of VLSI Systems

Explores the roles of testing in VLSI systems, different testing methodologies, cost analysis, factors affecting yield, and the importance of testing in modern technologies.

Testing of VLSI Systems

Explores defects, errors, and faults in VLSI systems, including fault models and testing challenges.

Fault Collapsing in VLSI Systems

Covers fault collapsing in VLSI systems to reduce redundancy and improve fault detection.

Simulation-Based Verification

Explores simulation-based verification in VLSI systems using compiled-code and event-driven algorithms.

Fault Simulation in VLSI Testing

Explores fault simulation in VLSI testing, covering fault coverage, fault models, algorithms, types of simulators, deductive simulation, and fault propagation rules.

Testability Analysis: SCOAP Measures

Introduces SCOAP measures for testability analysis in VLSI systems, covering controllability, observability, and test vector length prediction.

Test of VLSI Systems: ATPG and Fault Coverage

Explores test vector generation, ATPG algorithms, fault coverage, and path sensitization in VLSI systems.

Combinational and Sequential ATPG

Covers the D-calculus and implication procedures for fault detection in VLSI systems.

Design for Testability: Techniques and Hardware

Explores DFT techniques, scan design, JTAG boundary scan, and system test logic.

Built-In Self-Test (BIST): Techniques and Implementations

Explores Built-In Self-Test (BIST) techniques in VLSI systems, covering benefits, drawbacks, implementation details, and the use of Linear Feedback Shift Registers (LFSRs) for test pattern generation.

Response Compaction in VLSI Testing

Explores response compaction techniques in VLSI testing, including one's count compactor, transition count compactor, parity checking, LFSR, MISR, and BILBO.

Memory Cells Evolution

Explores the historical evolution of memory cells per chip and the increasing importance of memory in semiconductor markets.

Path-Delay Fault Testing

Covers linked and unlinked faults in VLSI systems, March test algorithms, critical paths, and path-delay fault testing.

VLSI Testing: Techniques and Economics

Explores test techniques for digital VLSI systems, covering fault modeling, test-pattern generation, and design for testability.

Testing of VLSI Systems

Explores defects, errors, and fault models in VLSI systems, emphasizing fault collapsing and dominance.

Simulation and Modeling in VLSI Systems

Explores simulation techniques and fault simulation procedures in VLSI systems.

Fault Simulation and Testability Analysis

Covers fault simulation, testability analysis, and fault list generation in VLSI systems.

Test of VLSI Systems: Combinational and Sequential ATPG

Covers the generation of test vector patterns, fault modeling, structural vs. functional tests, and the implementation of time-frame expansion.