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Lecture

Response Compaction in VLSI Testing

In course

EE-530: Test of VLSI systems

Test of VLSI Systems covers theoretical knowledge related to the major algorithms used in VLSI test, and design for test techniques. Basic knowledge related to computer-aided design for test techniques, and their integration into a design-flow are presente ...

Description

This lecture covers the analysis of the Circuit Under Test (CUT) response to test patterns in VLSI testing. It explains the challenges of handling large amounts of data generated by the CUT and introduces compaction techniques to reduce the data efficiently. The lecture discusses one's count compactor and transition count compactor methods, highlighting the principles and probability of fault masking. It also explores the concepts of parity checking, LFSR for response compaction, and multiple input signature register (MISR). The use of MISR for response compaction and the modular MISR example are presented, along with the analysis of LFSR signature and the built-in logic block observer (BILBO) for testing. The lecture concludes with discussions on test points and types of test points in VLSI testing.

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Instructor

Alexandre Schmid

Alexandre Schmid received the M.Sc. degree in microengineering and the Ph.D. degree in electrical engineering from the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, in 1994 and 2000, respectively. Since 1994, he has been with the EPFL, working with the Integrated Systems Laboratory as a Research and Teaching Assistant, and with the Electronics Laboratories as a Postdoctoral Fellow. In 2002, he was a Senior Research Associate with the Microelectronic Systems Laboratory, where he has been conducting research in the fields of bioelectronic interfaces and implantable biomedical electronics, nonconventional signal processing and neuromorphic hardware, and reliability of nanoelectronic devices, and also teaches with the Microengineering and Electrical Engineering Departments of EPFL. Since 2011, he is a Maître d'Enseignement et de Recherche (MER) Faculty Member with EPFL. He is a coauthor of two books, Reliability of Nanoscale Circuits and Systems, Methodologies and Circuit Architectures, Springer, 2011, and Wireless Cortical Implantable Systems, Springer, 2013, and a coeditor of one book, as well as over 100 articles published in journals and conferences. Dr. Schmid has served as the General Chair of the Fourth International Conference on Nano-Networks in 2009 and has been serving as an Associate Editor of the Institute of Electrical, Information, and Communication Engineers Electronics Express since 2009.

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