Copper TSV-Based Die-Level Via-Last 3D Integration Process with Parylene-C Adhesive Bonding Technique

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Publications associées (31)

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

Material and Electrical study of HfO2-Based Resistive Random Access Memories (ReRAMs)

Behnoush Attarimashalkoubeh

Resistive Random Access Memories (ReRAMs) have been researched intensively in the last past decades as a promising alternatives technology for the next-generation non-volatile memory (NVM) devices. ReRAMâ s excellent performance properties such as high sw ...

EPFL2019

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

Andreas Peter Burg, Andrea Bonetti

The rise of data-intensive applications has increased the demand for high-density and low-power embedded memories. Among them, the gain-cell embedded DRAM (GC-eDRAM) is a suitable alternative to the static random access memory (SRAM) due to its high memory ...

IEEE2019

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays

David Atienza Alonso, Ayse Kivilcim Coskun, Artem Andreev, Marina Zapater Sancho, Fulya Kaplan

Integrated flow cell array (FCA) is an emerging technology, targeting the cooling and power delivery challenges of modern 2D/3D Multi-Processor Systems-on-Chip (MPSoCs). In FCA, electrolytic solutions are pumped through microchannels etched in the silicon ...

2018

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

Babak Falsafi, Hamid Sarbazi-Azad, Mario Paulo Drumond Lages De Oliveira, Seyed Borna Ehsani

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, ...

2018

Learning-Based Hardware Design for Data Acquisition Systems

Cosimo Aprile

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conc ...

EPFL2018

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Javier Picorel Obando, Alexandros Daglis, Edouard Bugnion, Dmitrii Ustiugov, Mark Johnathon Sutherland, Dionysios Pnevmatikatos

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018

Optimized Memory Access For Dynamically Scheduled High Level Synthesis

Paolo Ienne, Atri Bhattacharyya

Dynamically-scheduled elastic circuits generated by High-Level Synthesis (HLS) tools are inherently out-of-order, following the flow of data rather than the evolution of an instruction pointer. Components of the circuit which access memory need to be conne ...

2018

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

Alexandre Sébastien Julien Levisse

As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resist ...

2018

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

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