Copper TSV-Based Die-Level Via-Last 3D Integration Process with Parylene-C Adhesive Bonding Technique

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The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

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As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resist ...

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Dynamically-scheduled elastic circuits generated by High-Level Synthesis (HLS) tools are inherently out-of-order, following the flow of data rather than the evolution of an instruction pointer. Components of the circuit which access memory need to be conne ...

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

Copper TSV-Based Die-Level Via-Last 3D Integration Process with Parylene-C Adhesive Bonding Technique

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A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Material and Electrical study of HfO2-Based Resistive Random Access Memories (ReRAMs)

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays

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Learning-Based Hardware Design for Data Acquisition Systems

RRAM Crossbar Arrays for Storage Class Memory Applications : Throughput and Density Considerations

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Optimized Memory Access For Dynamically Scheduled High Level Synthesis

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs