Metal-Ferroelectric-Metal-Oxide-Semiconductor Field Effect Transistor with Sub-60mV/decade Subthreshold Swing and Internal Voltage Amplification

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A signed analog precision Multiply-and-Accumulate (MAC) macro, targeted for edge computing, is introduced and fabricated in CMOS 28 nm technology. Scalability of Computing-in-memory (CIM) faces challenges due to complexities in implementing high bit-precision compute units. This work addresses scalability by pushing computations to analog domain and transferring data between MAC layers in a discrete time pipelined manner, removing the need for per-cycle memory read and write operations. The proposed analog

Dielectric Elastomer Actuators (DEAs) have a wide range of applications. They can be widely used in research to study cells under mechanical movement or stress. This is done by culturing the cells in vitro on the DEA and observing, under the microscope, the morphological and the numerous other important changes they are experiencing. However, in order to make sure that the effects observed on the cells are in fact from the mechanical stimuli alone, no other factors should be influencing the cells. Therefore

This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poisson’s equation including bandgap widening, intrinsic carrier-density scaling, and incomplete ionization. We demonstrate that accounting for incomplete ionization in the expression of the threshold voltage is critical for an accurate estimation of the current. The model is validated with our experimental results from nMOSFETs of a 28

In this paper, we report a detailed study of the negative capacitance field effect transistor (NCFET). We present the condition for the stabilization of the negative capacitance to achieve the voltage amplification across the active layer. The theory is based on Landauʼs theory of ferroelectrics combined with the surface potential model in all regimes of operation. We demonstrate the validity of the presented theory on experimental NCFETs using a gate stack made of P(VDF-TrFE) and SiO2. The proposed analyti

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Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primari

In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200MPa to 2GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.

In this chapter, we present the capabilities of the VHDL-AMS hardware description language for developing compact models. After a brief description of the VHDL-AMS language, we present two meaningful case studies on design oriented models of MOSFET. The first study focuses on the EKV v2.6 MOSFET model and takes into account the thermo-electrical interaction and the extrinsic aspects. The EKV v2.6 model uses linearization with respect to surface potential, resulting in physically well-based expressions for t

Data storage cells are formed on a substrate (13). Each of the data storage cells includes a field effect transistor with a source (18), drain (22) and gate (28) and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor and adjustment prevented by applying a voltage between the gate and drain and the source and the drain. An Independent claim is includ

Stress-induced changes in the imprint and switching behavior of (111)-oriented Pb(Zr,Ti)O-3 (PZT)-based capacitors have been studied using piezoresponse force microscopy. Visualization of polarization distribution and d(33)-loop measurements in individual 1x1.5-mum(2) capacitors before and after stress application, generated by substrate bending, provided direct experimental evidence of stress-induced switching. Mechanical stress caused elastic switching in capacitors with the direction of the resulting pol

The low aspect ratio of the mega amp spherical tokamak (MAST) allows differentiation between different forms of the H-mode threshold scaling. With optimized fuelling using inboard puffing, and a connected double null divertor (DND) magnetic configuration, the H-mode power threshold data lie about 1.7 times higher than recent scaling laws. Slight magnetic configuration changes, of the order of the ion Larmor radius, around a connected DND significantly influence H-mode access. H-mode confinement in discharge

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Piezoelectric response nonlinearity is approached using the Preisach description of hysteretic systems as collection of distributed bistable units. The Preisach model and its recent physical interpretation in terms of moving domain wall in a stochastically described pinning field are reviewed. It is shown that such an approach can effectively render not only the piezoelectric coefficient field dependences but also the field-response hysteresis, especially in the well-known case of linear piezoelectric field

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in t

In this communication we address two issues essential for low-voltage memory applications of ferroelectric thin films: the size effect on polarization switching, and polarization fatigue. According to the proposed concept, both of these phenomena are controlled by local injection of charge into the interfacial layers of the ferroelectric film. In the experimental part of this work, we show that the entrapped charge relaxation can be enhanced by introducing a thin RuO2 layer into the top interface of the Pt/

The effect of 1 MeV ion implantation on leakage conduction, dielectric and ferroelectric properties of the Pt/Pb(ZrxTi1-x)(2)O-3/Pt capacitors is studied for a wide range of implantation doses (10(10)-10(16) cm(-2)). It is shown that the implantation of Pt+, with an implant and vacancy profile peaking at the bottom interface and a dose within the range of 10(13)-10(16) cm(-2), provokes a strong suppression of the leakage conduction and ferroelectric hysteresis. In addition, ion implantation results in a dec

Today's world of electronics becomes more and more digital and therefore CMOS becomes the dominant technology. A CMOS process compared to a bipolar process offers several advantages, mainly a low power consumption which is important for portable systems powered by batteries or for large systems. Another point is the smaller device geometries, which increase the number of gates that can be packed on a single chip. Parallel to the increasing digital domain the analog field persists, because the origin of phys

Metal-Ferroelectric-Metal-Oxide-Semiconductor Field Effect Transistor with Sub-60mV/decade Subthreshold Swing and Internal Voltage Amplification

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