A Discrete-Time Analog Compute Macro for Edge ML with 200 TOPS/W in CMOS 28nm

A signed analog precision Multiply-and-Accumulate (MAC) macro, targeted for edge computing, is introduced and fabricated in CMOS 28 nm technology. Scalability of Computing-in-memory (CIM) faces challenges due to complexities in implementing high bit-precision compute units. This work addresses scalability by pushing computations to analog domain and transferring data between MAC layers in a discrete time pipelined manner, removing the need for per-cycle memory read and write operations. The proposed analog MAC circuit improves system energy-efficiency and latency by removing some of the complex operations in the conventional CIMs, such as partial-sum operations, data converters, shift and add, and memory access in multiple cycles. Due to its discrete-time nature, operation per-kernel can be scaled up as desired by tuning the supply voltage, making this work more suited for power-performance scalable Deep Neural Networks (DNNs). The proposed system achieves 200 TOPS/W and 6 GOPS per MAC in energy-efficient and high-performance modes respectively, enabling 10× and 30× improvement in energy efficiency and throughput over the state-of the-art MAC units with 8-bit operand precision.