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Pierre-Emmanuel Julien Marc Gaillardon

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Publications associées (119)

Towards the Use of Functionality-Enhanced Devices : A Transversal Design Approach

Pierre-Emmanuel Julien Marc Gaillardon

IEEE2014

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

Giovanni De Micheli, Jian Zhang, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar trans ...

Ieee-Inst Electrical Electronics Engineers Inc2013

3.5-D Integration: A Case Study

Giovanni De Micheli, Ciprian Seiculescu, Shashi Kanth Bobba, Vasileios Pavlidis, Pierre-Emmanuel Julien Marc Gaillardon

Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

2013

BDS-MAJ: A BDD-based Logic Synthesis Tool Exploiting Majority Logic Decomposition

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

Despite the impressive advance of logic synthesis during the past decades, a general methodology capable of efficiently synthesizing both control and datapath logic is still missing. Indeed, while synthe- sis techniques for random control logic (AND/OR-int ...

2013

Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: a Robustness Study

Giovanni De Micheli, Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Julien Marc Gaillardon

Vertically-stacked Silicon NanoWire FETs (SiN- WFETs) with gate-all-around control are the natural and most advanced extension of FinFETs. At advanced technology nodes, due to Schottky contacts at channel interfaces, devices show an ambipolar behavior, i.e ...

2013

A Fast TCAD-based Methodology for Variation Analysis of Emerging Nano-Devices

Giovanni De Micheli, Majid Yazdani, Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Julien Marc Gaillardon

Variability analysis of nanoscale transistors and circuits is emerging as a necessity at advanced technology nodes. Technology Computer Aided Design (TCAD) tools are powerful ways to get an accurate insight of Process Variations (PV). However ...

2013

Dual-threshold-voltage configurable circuits with three-independent gate silicon nanowire FETs

Giovanni De Micheli, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

We extend ambipolar silicon nanowire transistors by using three independent gates and show an efficient approach to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying dif ...

2013

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

We present a novel class of decision diagrams, called Biconditional Binary Decision Diagrams (BBDDs), that enable efficient logic synthesis for XOR-rich functions. BBDDs are binary decision diagrams where the Shannon’s expansion is replaced by the bicondit ...

2013

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

Emerging Non-Volatile Memories (eNVMs) such as Phase-Change RAMs (PCRAMs) or Oxide-based Resistive RAMs (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of buildin ...

Institute of Electrical and Electronics Engineers2013

SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT

Giovanni De Micheli, Catherine Lucie Jéromine Gasnier, Pierre-Emmanuel Julien Marc Gaillardon

Devices with controllable-polarity, such as Double-Gate Vertically-Stacked Nanowire FETs, have shown promising interests in recent years to implement XOR-based logic functions in an unprecedented compact way. Such a compactness is obtained at the cost of a ...

2013

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

2013

MIXSyn: An Efficient Logic Synthesis Methodology for Mixed XOR-AND/OR Dominated Circuits

Giovanni De Micheli, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

We present a new logic synthesis methodology, called MIXSyn, that produces area-efficient results for mixed XOR-AND/OR dominated logic functions. MIXSyn is a two step synthesis process. The first step is a hybrid logic optimization that enables selective a ...

2013

Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type charact ...

2013

Applications of Multi-Terminal Memristive Devices: A Review

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Davide Sacchetto, Sandro Carrara, Pierre-Emmanuel Julien Marc Gaillardon

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devi ...

Ieee-Inst Electrical Electronics Engineers Inc2013

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Pascal Andreas Meinerzhagen, Giovanni De Micheli, Davide Sacchetto, Andreas Peter Burg, Pierre-Emmanuel Julien Marc Gaillardon

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

GMS: Generic Memristive Structure for Non-Volatile FPGAs

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

The invention of the memristor enables new possibilities for computation and non-volatile memory storage. In this paper we propose a Generic Memristive Structure (GMS) for 3-D FPGA applications. The GMS cell is demonstrated to be utilized for steering logi ...

2012

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

2012

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of ...

2012

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properti ...

2011

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