Publications de Farzan Jazaeri

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In a MOSFET transistor, the subthreshold swing defines the switching efficiency, and the associated slope factor, or so-called body factor, is a critical parameter in charge-based models. However, in an advanced Fully -Depleted Silicon-On-Insulator (FDSOI) ...

Boltzmann relations are widely used in semiconductor physics to express the charge-carrier densities as a function of the Fermi level and temperature. However, these simple exponential relations only apply to sharp band edges of the conduction and valence ...

Relying on the previously developed charge-based approaches, this paper presents a physics-based design space of negative capacitance in double-gate and bulk MOSFET architectures. The impact of thickness variation of the ferroelectric on the DC characteris ...

Electrostatically confined quantum dots in semiconductors hold the promise to achieve high scalability and reliability levels for practical implementation of solid-state qubits where the electrochemical potentials of each quantum dot can be independently c ...

In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness ...

Taking into account the impact of self-heating and temperature rise effects, this work presents a physics-based analytical model for HEMTs, operating continuously from room temperature to high temperatures in linear and saturation regimes. Relying on the c ...

This brief reports the analytical modeling and measurements of the inflection in the MOSFET transfer characteristics at cryogenic temperatures. Inflection is the inward bending of the drain current versus gate voltage, which reduces the current in weak and ...

In this paper, we propose a physics-based compact model of the pinned photodiode (PPD) combined with the transfer gate. A set of analytical expressions is derived for the 2-D electrostatic profile, the PPD capacitance, and the charge transfer current. The ...

In this article, we present a closed-form solution for transcapacitances in GaN HEMTs derived from a design-oriented charge-based model of the AlGaAs/GaAs- and AlGaN/GaN-based HEMTs that were recently proposed. The analytical expressions are based on the c ...

This paper presents an in-depth DC characterization of a 22 nm FDSOI CMOS technology down to deep cryogenic temperature, i.e., 2.95 K. The impact of the back-gate voltage (V-back) on device performance, i.e., threshold voltage (V-T) and carrier transport, ...

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-n ...

The Large Hadron Collider (LHC) running at CERN will soon be upgraded to increase its luminosity giving rise to radiations reaching the level of GigaRad Total Ionizing Dose (TID). This paper investigates the impact of such high radiation on transistors fab ...

Nanowire field-effect transistor (NW FET) biosensors are known to be highly sensitive devices that can detect extremely low concentrations of biomolecules. In this article, we present an analytical model alongside with numerical simulations to calculate th ...

In this paper a commercial 28 nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device-phys ...

In this article, we present a theoretical analysis of a junctionless (JL), ion-sensitive, field-effect-transistor (ISFET), self-consistently combining the electrochemical interaction between the semiconductor-insulator interface and the surrounding electro ...

In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain ...

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is dev ...

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capac ...

Solid-state qubits can be implemented with electrostatically confined quantum dots in semiconductors, allowing gate voltages to independently control the electrochemical potentials of each quantum dot. Quantum dots offer high levels of reliability and scal ...

This brief proposes an analytical approach to model the DC electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistors (JL-NW-FETs). The model includes explicit expressions, taking into account the first-order perturb ...

Farzan Jazaeri

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An improved subthreshold swing expression accounting for back-gate bias in FDSOI FETs

Generalized Boltzmann relations in semiconductors including band tails

Design Space of Negative Capacitance in FETs

Tunneling Current Through a Double Quantum Dots System

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

High-Temperature HEMT Mode

Inflection Phenomenon in Cryogenic MOSFET Behavior

Compact Modeling of Charge Transfer in Pinned Photodiodes for CMOS Image Sensors

Transcapacitances in EPFL HEMT Model

Back-gate effects on DC performance and carrier transport in 22 nm FDSOI technology down to cryogenic temperatures

CJM: A Compact Model for Double-Gate Junction FETs

Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC

Design-Oriented Analytical Model for Nanowire Biosensors Including Dynamic Aspects

Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing

Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

Cryogenic MOS Transistor Model

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Design space of quantum dot spin qubits

Charge-based modeling of ultra narrow junctionless cylindrical nanowire FETs