Design Space of Negative Capacitance in FETs

Relying on the previously developed charge-based approaches, this paper presents a physics-based design space of negative capacitance in double-gate and bulk MOSFET architectures. The impact of thickness variation of the ferroelectric on the DC characteristics has been deeply investigated. The model precisely estimates a critical thickness of ferroelectric at instability conditions before the device goes into the hysteresis regime. Explicit relationships have been driven for hysteresis voltages which can be used as a general guideline for technology optimization of negative capacitance FETs.