Publications de Andreas Peter Burg

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Non-linearities introduced by the power amplifier stage can significantly reduce the performance of self-interference cancellation in full-duplex transceivers. Accordingly, we propose a full-duplex system architecture that predistorts the digital baseband ...

Multiple-input multiple-output (MIMO) detection algorithms providing soft information for a subsequent channel decoder pose significant implementation challenges due to their high computational complexity. In this paper, we show how sphere decoding can be ...

A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitl ...

Spatially-coupled low-density parity-check (SC-LDPC) codes are considered an important candidate for the upcoming 6G standardization, owing to their superior error-correction capability and practical decoding complexity. However, current high-throughput SC ...

LoRaWAN is one of the most popular low-power wide-area network (LPWAN) technologies. Its network architecture is based on a star-of-stars topology, in which LoRa nodes communicate with gateways that forward payloads to a central server when a packet detect ...

Inherently error-resilient applications in areas such as signal processing, machine learning and data analytics provide opportunities for relaxing reliability requirements, and thereby reducing the overheads incurred by conventional error correction scheme ...

A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomi ...

This paper describes the implementation of the complete baseband processing of an IEEE 802.11a receiver on a design-framework for application specific processors. The underlying generic architecture is described, the computational kernels required for an I ...

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

n this paper we present an architecture for an MMSE ﬁlter matrix computation unit for signal detection in MIMO-OFDM communication systems. We propose to compute the required matrix inverse based on a Cholesky decomposition, followed by a Gauss-Jordan matri ...

Polar codes are a recent family of error-correcting codes with a number of desirable characteristics. Their disruptive nature is illustrated by their rapid adoption in the 5 th-generation mobile-communication standard, where they are used to protect contro ...

Embedded biosignal analysis involves a considerable amount of parallel computations, which can be exploited by employing low-voltage and ultra-low-power (ULP) parallel computing architectures. By allowing data and instruction broadcasting, single instructi ...

The development of state-of-the-art wireless communication transceivers in semiconductor technology is a challenging process due to complexity and stringent requirements of modern communication standards such as IEEE 802.11n. This tutorial paper describes ...

In this paper, a low complexity system for spectral analysis of heart rate variability (HRV) is presented. The main idea of the proposed approach is the implementation of the Fast-Lomb periodogram that is a ubiquitous tool in spectral analysis, using a wav ...

In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the ...

Due to the low-latency and high-reliability require-ments of 5G, low-complexity node-based successive cancellation list (SCL) decoding has received considerable attention for use in 5G communications systems. By identifying special constituent codes in the ...

Turbo codes have been successfully adopted in 4G LTE, which can approach the channel capacity with Bahl-Cocke-Jelinek-Raviv (BCJR) decoding. With the evolution from 4G LTE to 5G NR, there is a demand to design a unified channel decoder that supports both L ...

Modern trains act as Faraday cages making it challenging to provide high cellular data capacities to passengers. A solution is the deployment of linear cells along railway tracks, forming a cellular corridor. To provide a sufficiently high data capacity, m ...

LoRa is a popular low-power wide-area network (LPWAN) technology that uses spread-spectrum to achieve long-range connectivity and resilience to noise and interference. For energy efficiency reasons, LoRa adopts a pure ALOHA access scheme, which leads to re ...

Multilevel gain-cell DRAMs are interesting to improve the area-efficiency of modern fault-tolerant systems-on-chip implemented in deep-submicron CMOS technologies. This paper addresses the problem of long access times in such multilevel gain-cell DRAMs, wh ...

Andreas Peter Burg

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Digital Predistortion of Power Amplifier Non-Linearities for Full-Duplex Transceivers

Soft-output sphere decoding: Performanceand implementation aspects

Fin field-effect transistor (finfet) based semiconductor memory array having memory cells with a reduced surface area

Towards 6G: Configurable High-Throughput Decoder Implementation for SC-LDPC Codes

Increasing LoRa Sensitivity and Reliability with an IoT Cloud RAN

Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

An IEEE 802.11a baseband receiver implementation on an application specific processor

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Block-Floating-Point Enhanced MMSE Filter Matrix Computation for MIMO-OFDM Communication Systems

On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes

Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

Simulation and Emulation of MIMO Wireless Baseband Transceivers

Low Complexity Spectral Analysis of Heart-Rate-Variability through a Wavelet Based FFT

Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation

Improved Belief Propagation Decoding of Turbo Codes

Increasing Cellular Network Energy Efficiency for Railway Corridors

A Maximum-Likelihood-based Multi-User LoRa Receiver Implemented in GNU Radio

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM