Davide Sacchetto

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Publications associées (52)

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Michail Zervas, Andreea Veronica Savu, Davide Sacchetto, Shenqi Xie

We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub ...

Elsevier2012

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of ...

2012

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Andreea Veronica Savu, Davide Sacchetto

We report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si ...

Elsevier2011

New Insight on Bio-sensing by Nano-fabricated Memristors

Yusuf Leblebici, Giovanni De Micheli, Davide Sacchetto, Sandro Carrara

We report here on a new insight for bio-sensing based on the memristive effect of functionalized Schottky-barrier memristive silicon nanowire in dry environment. The device concept is discussed. Electrical measurements confirm the bio-detection by the narr ...

2011

Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Michail Zervas, Andreea Veronica Savu, Davide Sacchetto, Shenqi Xie

2011

Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications

Yusuf Leblebici, Davide Sacchetto, Izzet Yildiz

The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical-mechanical-po ...

Institute of Physics2011

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Davide Sacchetto

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fab ...

Elsevier2011

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properti ...

2011

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto

Next generation logic switch devices are ex- pected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that ar ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Andreea Veronica Savu, Davide Sacchetto

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micro ...

2010

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangem ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2010

Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays

Yusuf Leblebici, Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto

We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer ...

2009

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