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Davide Sacchetto

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Publications associées (52)

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Heterogeneous Integration of ReRAM Crossbars in 180nm CMOS BEoL Process

Yusuf Leblebici, Giovanni De Micheli, Davide Sacchetto, Jury Sandrini, Pierre-Emmanuel Julien Marc Gaillardon, Tugba Demirci, Maxime Victor Thammasack

This work reports on a heterogeneous integration of resistive memories into the Back-End-of-the-Line of 180nm standard CMOS foundry chips. A TaOx-based ReRAM technology with materials and processes fully CMOS compatible has been developed and characterized ...

Elsevier2015

Monolithic Fabrication of Silicon Nanowires Bridging Thick Silicon Structures

Yusuf Leblebici, Oliver Peric, Davide Sacchetto, Zuhal Tasdemir

A monolithic process is developed for the fabrication of Si nanowires within thick Si substrates. A combination of anisotropic etch and sidewall passivation is utilized to protect and release Si lines during the subsequent deep etch. An etch depth of 10 mu ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Memristive-Biosensors: A New Detection Method by Using Nanofabricated Memristors

Yusuf Leblebici, Giovanni De Micheli, Davide Sacchetto, Sandro Carrara, Camilla Baj-Rossi

This paper proposes a new detection methodology based on memristive-effect registered on silicon nanowire. The nano-wires are fabricated by a lithographic technique that allows precise and selective etching at the nanoscale. The wires are obtained in three ...

Elsevier2012

Progression towards high efficiency perovskite solar cells via optimisation of the front electrode and blocking layer

Christophe Ballif, Sylvain Nicolay, Soo-Jin Moon, Arnaud Walter, Davide Sacchetto, Björn Niesen, Matthias Wolfgang Bräuninger

The effects of a fluorine doped tin oxide (FTO) electrode, titanium dioxide (TiO2-x) blocking layer (BL) and perovskite (methyl ammonium lead triiodide) preparation on the overall properties of the photovoltaic cells have been studied. The FTO electrode wa ...

Royal Society of Chemistry2016

Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Yüksel Temiz, Davide Sacchetto

In this letter we report on the fabrication and characterization of titanium dioxide (TiO2)-based resistive RAM (ReRAM) co-integration with 380 ìm-height Cu Through Silicon Via (TSV) arrays for programmable 3D interconnects. Nonvolatile resistive switching ...

Institute of Electrical and Electronics Engineers2012

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

Institute of Electrical and Electronics Engineers2014

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

Emerging Non-Volatile Memories (eNVMs) such as Phase-Change RAMs (PCRAMs) or Oxide-based Resistive RAMs (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of buildin ...

Institute of Electrical and Electronics Engineers2013

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jury Sandrini, Pierre-Emmanuel Julien Marc Gaillardon, Tugba Demirci, Maxime Victor Thammasack

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

Institute of Electrical and Electronics Engineers2016

Fully textured monolithic perovskite/silicon tandem solar cells with 25.2% power conversion efficiency

Christophe Ballif, Laura Ding, Sylvain Nicolay, Quentin Thomas Jeangros, Davide Sacchetto, Mathieu Gérard Boccard, Matthieu Despeisse, Jérémie Werner, Florent Sahli, Loris Barraud, Raphaël Monnard, Gianluca Cattaneo, Bertrand Yves Paul Paviet-Salomon, Björn Niesen, Matthias Wolfgang Bräuninger

Tandem devices combining perovskite and silicon solar cells are promising candidates to achieve power conversion efficiencies above 30% at reasonable costs. State-of-the-art monolithic two-terminal perovskite/silicon tandem devices have so far featured sil ...

2018

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Yusuf Leblebici, Pascal Andreas Meinerzhagen, Giovanni De Micheli, Davide Sacchetto, Andreas Peter Burg, Pierre-Emmanuel Julien Marc Gaillardon

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT

Institute of Electrical and Electronics Engineers2014

Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

Yusuf Leblebici, Jürgen Brugger, Giovanni De Micheli, Andreea Veronica Savu, Davide Sacchetto

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micro ...

2010

Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability

Yusuf Leblebici, Giovanni De Micheli, Davide Sacchetto

In this letter, we report on the fabrication and characterization of ambipolar silicon-nanowire (SiNW) field-effect transistors (FETs) with a double-independent-gate (DIG) structure for polarity control. Several structures are fabricated, showing the effec ...

Institute of Electrical and Electronics Engineers2012

Efficient Near-Infrared-Transparent Perovskite Solar Cells Enabling Direct Comparison of 4-Terminal and Monolithic Perovskite/Silicon Tandem Cells

Christophe Ballif, Sylvain Nicolay, Soo-Jin Moon, Arnaud Walter, Davide Sacchetto, Nicolas Tétreault, Stefaan De Wolf, Matthieu Despeisse, Jérémie Werner, Florent Sahli, Loris Barraud, Bertrand Yves Paul Paviet-Salomon, Björn Niesen, Matthias Wolfgang Bräuninger

Combining market-proven silicon solar cell technology with an efficient wide band gap top cell into a tandem device is an attractive approach to reduce the cost of photovoltaic systems. For this, perovskite solar cells are promising high-efficiency top cel ...

Amer Chemical Soc2016

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Yusuf Leblebici, Clemens Benedict Nyffeler, Davide Sacchetto, Seniz Esra Küçük

In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...

2014

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

2012

Applications of Multi-Terminal Memristive Devices: A Review

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Davide Sacchetto, Sandro Carrara, Pierre-Emmanuel Julien Marc Gaillardon

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devi ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Hybrid sequential deposition process for fully textured perovskite/silicon tandem solar cells

Christophe Ballif, Laura Ding, Sylvain Nicolay, Quentin Thomas Jeangros, Soo-Jin Moon, Arnaud Walter, Davide Sacchetto, Mathieu Gérard Boccard, Matthieu Despeisse, Jérémie Werner, Florent Sahli, Loris Barraud, Raphaël Monnard, Monica Morales Masis, Gianluca Cattaneo, Bertrand Yves Paul Paviet-Salomon, Björn Niesen, Gizem Nogay, Oscar Esteban Rucavado Leandro, Matthias Wolfgang Bräuninger, Peter Joseph Fiala, Chien-Jen Yang, Fan Fu

Tandem solar cells that feature a high-bandgap perovskite cell on top of a lower bandgap silicon cell have the potential to reach efficiencies > 30%. Here, we present a versatile hybrid deposition method that yields conformal perovskite cells directly on t ...

IEEE2018

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Davide Sacchetto, Jury Sandrini, Pierre-Emmanuel Julien Marc Gaillardon, Tugba Demirci

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...

2014

Zinc tin oxide as high-temperature stable recombination layer for mesoscopic perovskite/silicon monolithic tandem solar cells

Christophe Ballif, Sylvain Nicolay, Soo-Jin Moon, Arnaud Walter, Davide Sacchetto, Stefaan De Wolf, Xavier Niquille, Jérémie Werner, Monica Morales Masis, Björn Niesen, Philipp Friedrich Hermann Löper, Oscar Esteban Rucavado Leandro

Perovskite/crystalline silicon tandem solar cells have the potential to reach efficiencies beyond those of silicon single-junction record devices. However, the high-temperature process of 500 °C needed for state-of-the-art mesoscopic perovskite cells has, ...

American Institute of Physics2016

Top-Down Fabrication of Silicon Nanowires in Ultra-deep Trenches

Yusuf Leblebici, Oliver Peric, Davide Sacchetto, Zuhal Tasdemir, Georg Fantner

One-Dimensional (1D) nanostructures have gained a considerable attention in the field of semiconductor technology for the past several decades. With the help of rapid development in the process technology, it becomes possible to scale these nanostructures ...

2014