Publications de Davide Sacchetto

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This paper proposes a new detection methodology based on memristive-effect registered on silicon nanowire. The nano-wires are fabricated by a lithographic technique that allows precise and selective etching at the nanoscale. The wires are obtained in three ...

In this letter we report on the fabrication and characterization of titanium dioxide (TiO2)-based resistive RAM (ReRAM) co-integration with 380 ìm-height Cu Through Silicon Via (TSV) arrays for programmable 3D interconnects. Nonvolatile resistive switching ...

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

Emerging Non-Volatile Memories (eNVMs) such as Phase-Change RAMs (PCRAMs) or Oxide-based Resistive RAMs (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of buildin ...

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micro ...

In this letter, we report on the fabrication and characterization of ambipolar silicon-nanowire (SiNW) field-effect transistors (FETs) with a double-independent-gate (DIG) structure for polarity control. Several structures are fabricated, showing the effec ...

In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devi ...

Tandem solar cells that feature a high-bandgap perovskite cell on top of a lower bandgap silicon cell have the potential to reach efficiencies > 30%. Here, we present a versatile hybrid deposition method that yields conformal perovskite cells directly on t ...

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...

One-Dimensional (1D) nanostructures have gained a considerable attention in the field of semiconductor technology for the past several decades. With the help of rapid development in the process technology, it becomes possible to scale these nanostructures ...

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fab ...

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type charact ...

A bipolar resistive switching device including an electrically conductive bottom electrode, a stack of transition metal oxides layers, a number of transition metal oxide layers being equal or greater than 2, the stack including: at least one MOx layer, at ...

After decades of miniaturization and performance tuning, Silicon electronics is approaching its technological limits. In the search for alternative transistor channel materials, Graphene has been given much attention since its discovery in 2004, mainly bec ...

We demonstrate multiple silicon-nitride nanophotonic elements for on-chip processing of octave-spanning microresonator frequency combs. Dichroic filters, multimode interferometers, and tunable add-drop microring filters are shown along with soliton microco ...

Davide Sacchetto

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Memristive-Biosensors: A New Detection Method by Using Nanofabricated Memristors

Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Applications of Multi-Terminal Memristive Devices: A Review

Hybrid sequential deposition process for fully textured perovskite/silicon tandem solar cells

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

Top-Down Fabrication of Silicon Nanowires in Ultra-deep Trenches

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited

Resistive Switching Element and Use Thereof

Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography

Graphene Field Effect Devices Operating in Differential Configuration

Integrated Photonic Interposers for Processing Octave-Spanning Microresonator Frequency Combs