Recherche

Afficher tous les résultats pour

Accueil

Personne

Davide Sacchetto

À propos
Confidentialité
Mentions légales

Graph Chatbot

Publications associées (52)

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Institute of Electrical and Electronics Engineers2014

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Davide Sacchetto, Jury Sandrini, Pierre-Emmanuel Julien Marc Gaillardon, Tugba Demirci

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...

2014

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Yusuf Leblebici, Clemens Benedict Nyffeler, Davide Sacchetto, Seniz Esra Küçük

In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...

2014

Memristive Biosensors Under Varying Humidity Conditions

Yusuf Leblebici, Giovanni De Micheli, Davide Sacchetto, Sandro Carrara, Camilla Baj-Rossi, Francesca Puppo, Akshat Dave

We attempt to examine the potential of silicon nanowire memristors in the field of nanobiosensing. The mem- ristive devices are crystalline Silicon (Si) Nanowires (NWs) with Nickel Silicide (NiSi) terminals. The nanowires are fabricated on a Silicon-on-Ins ...

Institute of Electrical and Electronics Engineers2014

Top-Down Fabrication of Silicon Nanowires in Ultra-deep Trenches

Yusuf Leblebici, Oliver Peric, Davide Sacchetto, Zuhal Tasdemir, Georg Fantner

One-Dimensional (1D) nanostructures have gained a considerable attention in the field of semiconductor technology for the past several decades. With the help of rapid development in the process technology, it becomes possible to scale these nanostructures ...

2014

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

Institute of Electrical and Electronics Engineers2014

Ambipolar silicon nanowire field effect transistor

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto

This invention describes a novel electronic device consisting of one-or more-vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central se ...

2013

Applications of Multi-Terminal Memristive Devices: A Review

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Davide Sacchetto, Sandro Carrara, Pierre-Emmanuel Julien Marc Gaillardon

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devi ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type charact ...

2013

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

2013

Multi-Terminal Am-Bipolar Memristive Devices for Emerging Logic and Memory Architectures

Davide Sacchetto

EPFL2013

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Pascal Andreas Meinerzhagen, Giovanni De Micheli, Davide Sacchetto, Andreas Peter Burg, Pierre-Emmanuel Julien Marc Gaillardon

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

Emerging Non-Volatile Memories (eNVMs) such as Phase-Change RAMs (PCRAMs) or Oxide-based Resistive RAMs (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of buildin ...

Institute of Electrical and Electronics Engineers2013

GMS: Generic Memristive Structure for Non-Volatile FPGAs

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon

The invention of the memristor enables new possibilities for computation and non-volatile memory storage. In this paper we propose a Generic Memristive Structure (GMS) for 3-D FPGA applications. The GMS cell is demonstrated to be utilized for steering logi ...

2012

Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability

Yusuf Leblebici, Giovanni De Micheli, Davide Sacchetto

In this letter, we report on the fabrication and characterization of ambipolar silicon-nanowire (SiNW) field-effect transistors (FETs) with a double-independent-gate (DIG) structure for polarity control. Several structures are fabricated, showing the effec ...

Institute of Electrical and Electronics Engineers2012

Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics

Yusuf Leblebici, Giovanni De Micheli, Michail Zervas, Yüksel Temiz, Davide Sacchetto

In this letter we report on the fabrication and characterization of titanium dioxide (TiO2)-based resistive RAM (ReRAM) co-integration with 380 ìm-height Cu Through Silicon Via (TSV) arrays for programmable 3D interconnects. Nonvolatile resistive switching ...

Institute of Electrical and Electronics Engineers2012

Memristive-Biosensors: A New Detection Method by Using Nanofabricated Memristors

Yusuf Leblebici, Giovanni De Micheli, Davide Sacchetto, Sandro Carrara, Camilla Baj-Rossi

This paper proposes a new detection methodology based on memristive-effect registered on silicon nanowire. The nano-wires are fabricated by a lithographic technique that allows precise and selective etching at the nanoscale. The wires are obtained in three ...

Elsevier2012

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

2012

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Yusuf Leblebici, Giovanni De Micheli, Davide Sacchetto

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal dev ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Page 2 sur 3