Publications de Davide Sacchetto

Publications associées (52)

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Giovanni De Micheli, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Jian Zhang, Michele De Marchi

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the ...

Institute of Electrical and Electronics Engineers2014

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Giovanni De Micheli, Yusuf Leblebici, Jürgen Brugger, Andreea Veronica Savu, Davide Sacchetto, Michail Zervas, Shenqi Xie

We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub ...

Elsevier2012

ITO/MoOx/a-Si:H(i) Hole-Selective Contacts for Silicon Heterojunction Solar Cells: Degradation Mechanisms and Cell Integration

Christophe Ballif, Matthieu Despeisse, Aïcha Hessler-Wyser, Sylvain Nicolay, Quentin Thomas Jeangros, Antoine Descoeudres, Davide Sacchetto, Loris Barraud, Gabriel Christmann, Jonas Geissbühler

Molybdenum oxide is an efficient hole collector for silicon solar cells. However, its optoelectronic properties deteriorate during cell manufacturing. To assess this issue, the optoelectronic properties and microstructure of molybdenum oxide-based hole con ...

2017

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Giovanni De Micheli, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Davide Sacchetto, Shashi Kanth Bobba, Michele De Marchi

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

2013

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Giovanni De Micheli, Yusuf Leblebici, Jürgen Brugger, Andreea Veronica Savu, Davide Sacchetto

We report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si ...

Elsevier2011

Memristive Biosensors Under Varying Humidity Conditions

Giovanni De Micheli, Yusuf Leblebici, Sandro Carrara, Davide Sacchetto, Camilla Baj-Rossi, Francesca Puppo

We attempt to examine the potential of silicon nanowire memristors in the field of nanobiosensing. The mem- ristive devices are crystalline Silicon (Si) Nanowires (NWs) with Nickel Silicide (NiSi) terminals. The nanowires are fabricated on a Silicon-on-Ins ...

Institute of Electrical and Electronics Engineers2014

Graphene Field Effect Devices Operating in Differential Circuit Configuration

Yusuf Leblebici, Davide Sacchetto, Clemens Benedict Nyffeler

We study the concept of a basic building block for circuits using differential signaling and being based on graphene field effect devices. We fabricated a number of top-gated graphene FETs using commercially available graphene and employing electron beam l ...

Elsevier2015

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Giovanni De Micheli, Yusuf Leblebici, Davide Sacchetto

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal dev ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Giovanni De Micheli, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Jian Zhang, Michele De Marchi

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Institute of Electrical and Electronics Engineers2014

Towards integrated photonic interposers for processing octave-spanning microresonator frequency combs

Davide Sacchetto, Michail Zervas, Michael Wolfgang Geiselmann

Microcombs-optical frequency combs generated in microresonators-have advanced tremendously in the past decade, and are advantageous for applications in frequency metrology, navigation, spectroscopy, telecommunications, and microwave photonics. Crucially, m ...

SPRINGERNATURE2021

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Davide Sacchetto, Yusuf Leblebici, Tugba Demirci

A non-volatile latch circuitry, comprising a Re RAM cell configured to store a final value of the non-volatile latch circuitry; a data selection circuitry configured to connect or disconnect a data input to a plus voltage node and a minus voltage node of t ...

2014

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

Giovanni De Micheli, Yusuf Leblebici, Davide Sacchetto, Mohamed Haykel Ben Jamaa

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangem ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2010

Multi-Terminal Am-Bipolar Memristive Devices for Emerging Logic and Memory Architectures

Davide Sacchetto

EPFL2013

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Giovanni De Micheli, Yusuf Leblebici, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Michele De Marchi

We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of ...

2012

Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications

Yusuf Leblebici, Davide Sacchetto

The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical-mechanical-po ...

Institute of Physics2011

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

Giovanni De Micheli, Yusuf Leblebici, Davide Sacchetto, Michele De Marchi

Next generation logic switch devices are ex- pected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that ar ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Ambipolar silicon nanowire field effect transistor

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Michele De Marchi

This invention describes a novel electronic device consisting of one-or more-vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central se ...

2013

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Giovanni De Micheli, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Mohamed Haykel Ben Jamaa

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properti ...

2011

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Luca Gaetano Amarù, Michele De Marchi, Shashi Kanth Bobba

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014