Publications de Davide Sacchetto

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The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the ...

We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub ...

Molybdenum oxide is an efficient hole collector for silicon solar cells. However, its optoelectronic properties deteriorate during cell manufacturing. To assess this issue, the optoelectronic properties and microstructure of molybdenum oxide-based hole con ...

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

We report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si ...

We attempt to examine the potential of silicon nanowire memristors in the field of nanobiosensing. The mem- ristive devices are crystalline Silicon (Si) Nanowires (NWs) with Nickel Silicide (NiSi) terminals. The nanowires are fabricated on a Silicon-on-Ins ...

We study the concept of a basic building block for circuits using differential signaling and being based on graphene field effect devices. We fabricated a number of top-gated graphene FETs using commercially available graphene and employing electron beam l ...

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Microcombs-optical frequency combs generated in microresonators-have advanced tremendously in the past decade, and are advantageous for applications in frequency metrology, navigation, spectroscopy, telecommunications, and microwave photonics. Crucially, m ...

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal dev ...

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangem ...

We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of ...

The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical-mechanical-po ...

Next generation logic switch devices are ex- pected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that ar ...

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properti ...

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

This work reports on a heterogeneous integration of resistive memories into the Back-End-of-the-Line of 180nm standard CMOS foundry chips. A TaOx-based ReRAM technology with materials and processes fully CMOS compatible has been developed and characterized ...

A monolithic process is developed for the fabrication of Si nanowires within thick Si substrates. A combination of anisotropic etch and sidewall passivation is utilized to protect and release Si lines during the subsequent deep etch. An etch depth of 10 mu ...

Davide Sacchetto

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A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

ITO/MoOx/a-Si:H(i) Hole-Selective Contacts for Silicon Heterojunction Solar Cells: Degradation Mechanisms and Cell Integration

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Memristive Biosensors Under Varying Humidity Conditions

Graphene Field Effect Devices Operating in Differential Circuit Configuration

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Towards integrated photonic interposers for processing octave-spanning microresonator frequency combs

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

Multi-Terminal Am-Bipolar Memristive Devices for Emerging Logic and Memory Architectures

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications

Alternative Design Methodologies for the Next Generation Logic Switch (invited paper)

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Nanowire systems: technology and design (invited paper)

Heterogeneous Integration of ReRAM Crossbars in 180nm CMOS BEoL Process

Monolithic Fabrication of Silicon Nanowires Bridging Thick Silicon Structures