Publications de Yusuf Leblebici

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The Panoptic camera is an omnidirectional multi-aperture visual system which is realized by mounting multiple imaging sensors on a hemispherical frame. In this chapter, we will present a novel distributed and parallel implementation of the real-time omnidi ...

For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-based receiver (RX) has become a dominant architecture due to its strong equalization capability using complex digital signal processing algorithm benefiting from th ...

This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient ...

In this paper we present an electrical model of the inner hair cell based on an improved mathematical model. The model is implemented in silicon in the current domain using translinear circuits. It improves on previous models by taking into consideration t ...

In this paper, a die-level CMOS post-processing scheme for 3D integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The ...

Single photon detection at telecom wavelengths is of importance in many industrial applications ranging from quantum cryptography, quantum optics, optical time domain reflectometry, non-invasive testing of VLSI circuits, eye-safe LIDAR to laser ranging. In ...

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can sa ...

3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between processing cores, and an effective way to diminish this impact on communica ...

This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-dig ...

One of the most critical challenges for nanofluids in practical applications is related to their stability and reusability since a gradual agglomeration of nanoparticles in nanofluids occurs with time and is accelerated by heating. In this study, we propos ...

This review provides a high-level synthesis of significant recent advances in artificial neural network research, as well as multi-disciplinary concepts connected to the far-reaching goal of obtaining intelligent systems. We assume that a global outlook of ...

A time-division multiplexing (TDM) digital channel coding scheme for wireline multi-drop interfaces has been proposed. Shaping the TX spectrum to avoid channel frequency notches, the proposed digital TDM signaling reduces inter-symbol interference (ISI) an ...

New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation highperformance computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs, supplying electrical power to the computing equipment and constantly removing the generated heat is rapidly becoming the dominant cost in any HPC facility. Thus, both power and thermal/cooling implications play a major role in the

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Surface functionalization of 1D materials such as silicon nanowires is a critical preparation technology for biochemical sensing. However, existing nonselective functionalization techniques result in nonlocal binding and contamination, with potential devic ...

In thiswork,we present aminiaturized high definition vision system inspired by insect eyes, with a distributed illumination method, which can work in dark environments for proximity imaging applications such as endoscopy. Our approach is based on modeling ...

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal dev ...

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units on top of each ot

In ultra-low-power (ULP) applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, re ...

The real-time development of multi-camera systems is a great challenge. Synchronization and large data rates of the cameras adds to the complexity of these systems as well. The complexity of such system also increases as the number of their incorporating cameras increases. The customary approach to implementation of such system is a central type, where all the raw stream from the camera are first stored then processed for their target application. An alternative approach is to embed smart cameras to these s

Yusuf Leblebici

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Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

A silicon model of the inner hair cell

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

ASIC for High-Speed-Gating and Free Running Operation of SPADs

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Through Silicon Via-Based Grid for Thermal Control in 3D Chips

A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI

Increasing the stability of nanofluids with cavitating flows in micro orifices

Review of Advances in Neural Networks: Neural Design Technology Stack

A Time-Division Multiplexing Signaling Scheme for Low-Power Multi-Drop Memory Links

Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Stencil-Based Selective Surface Functionalization of Silicon Nanowires in 3D Device Architectures for Next-Generation Biochemical Sensors

An Insect Eye Inspired Miniaturized Multi-Camera System for Endoscopic Imaging

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Dynamic thermal management in 3D multicore architectures

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

Interconnected Network of Cameras