Publications de Yusuf Leblebici

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A new circuit style is proposed to tune the delay, subthreshold leakage (ISUB), and gate leakage (IG) of high fan-in multiplexer circuits, such as the FPGA Look-Up Table (LUT) and Switch-Box (SB), without increasing the Gate Induced Drain Leakage (GIDL) cu ...

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

This paper presents a via-programmable expanded universal logic gate in MOS current-mode logic which can implement any 3-input Boolean function, and a significant subset of 4-input and 5-input functions. The universal logic gate is programmed with the firs ...

Silica nanowires spanning 10 μm-deep trenches are fabricated from different types of silsesquioxane-based precursors by direct e-beam patterning on silicon followed by release through deep reactive ion etching. Nanowire aspect ratios as large as 150 are ac ...

We assess the impact of the conductance response of Non-Volatile Memory (NVM) devices employed as the synaptic weight element for on-chip acceleration of the training of large-scale artificial neural networks (ANN). We briefly review our previous work towa ...

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. ...

In-memory computing with nanoscale memristive devices such as phase-change memory (PCM) has emerged as an alternative to conventional von Neumann systems to train deep neural networks (DNN) where a synaptic weight is represented by the device conductance. ...

The theoretical analysis of R-fold modular redundancy with distributed voters - distributed R-fold modular redundancy in terms of reliability is presented for the first time to the best of author's knowledge. This technique is compared in terms of resistan ...

Journal article A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder: A Katic, Nikola; Cojbasic, Radisav; Schmid, Alexandre; Leblebici, Yusuf Published in: Microelectronics Journal (ISSN: 0026-2692), vol. 46, num. 12, ...

Surface-tension-driven self-alignment (SA) is a promising technique for heterogeneous die-level stacking. Multiple dies can be manipulated in parallel at minimal cost. A defined amount of water present between the die and a carrier substrate is used to ali ...

In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control l ...

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...

A very low power mixed-signal design methodology based on subthreshold source-coupled circuits is presented, and a nano-Watt range analog-to-digital converter (ADC) circuit based on folding-interpolating topology is proposed as a complete design example. T ...

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

In this paper we present the design of a temperature compensated low-tune-voltage-sensitive CMOS ring oscillator in 40nm standard CMOS technology. The oscillator has an overall frequency range from 3.1 GHz to 3.6 GHz. The effect of temperature variations o ...

An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alt ...

Stereo image rectification is a pre-processing step of disparity estimation intended to remove image distortions and to enable stereo matching along an epipolar line. A real-time disparity estimation system needs to perform real-time rectification which re ...

A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS tra ...

Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patt ...

Yusuf Leblebici

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A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Via-Programmable Expanded Universal Logic Gate in MCML for Structured ASIC Applications: Circuit Design

Superplastic behavior of silica nanowires obtained by direct patterning of silsesquioxane-based precursors

Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: impact of conductance response

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

Impact of conductance drift on multi-PCM synaptic architectures

Optimization of Nanoelectronic Systems Reliability under Massive Defect Density Using Distributed R-Fold Modular Redundancy

A Sub-mW Pulse-Based 5-bit Flash ADC with a Time-Domain Fully-Digital Reference Ladder

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

3.6 GHz CMOS Ring Oscillator with Low Tune Voltage Sensitivity and Temperature Compensation

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Compressed look-up-table based real-time rectification hardware

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Complete Nanowire Crossbar Framework Optimized for the Multi-Spacer Patterning Technique