Publications de Yusuf Leblebici

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High dynamic range (HDR) images are usually obtained by capturing several images of the scene at different exposures. Previous HDR video techniques adopted the same principle by stacking HDR frames in time domain. We designed a new multi-camera platform wh ...

Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PLA) can be built out of these devices, and we illustrate how they outperform u ...

Defects in MOSFET oxides are a major issue in CMOS technologies, affecting not only the device electrical performances but also compromising reliability and endurance. Using Charge-Pumping and C-V measurements, defects have been characterized in native and electrically-aged oxides. These electrical measurements have been compared to the predictions of advanced simulations, accounting for multi-phonon assisted emission/capture rates and including the presence of multiple defects and the contribution of elect

3-D integration is a promising prospect for implementing high performance multifunctional systems-on- chip. Through Silicon Vias (TSVs) are the enablers for achieving high bandwidth paths in inter-plane communications. TSVs also provide higher vertical lin ...

This article presents the analysis of the power efficiency of the inductive links used for remote powering of the biomedical implants by considering the effect of the load resistance on the efficiency. The optimum load condition for the inductive links is calculated from the analysis and the coils are optimized accordingly. A remote powering link topology with a matching network between the inductive link and the rectifier has been proposed to operate the inductive link near its optimum load condition to im

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micro ...

This paper reports on the fabrication and characterization of a pA current and temperature sensing device with ultra-low power consumption based on a Schottky barrier silicon nanowire transistor. Thermionic and trap-assisted tunneling current conduction mechanisms are identified and discussed on the base of the device sensitivity upon current and temperature biasing. In particular, very low current sensing properties are confirmed also with previously reported polysilicon- channel nanowire Schottky barrier

In this paper, we study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages.We show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly ...

This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the reference frequency and delivers differential inphase (I) and quadrature (Q) clocks by generating 8 equally spaced clock phases and combining these phases appropriately. A technique for reducing deterministic jitter (DJ) in MDLL is proposed. The prototype dissipat

This paper proposes an unconventional image acquisition scheme for machine vision applications, based on detecting ratios of illumination (pixel) intensities. Detecting relative ratios enables capturing the scene features and patterns almost independently ...

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approac ...

In this letter, we report on the fabrication and characterization of ambipolar silicon-nanowire (SiNW) field-effect transistors (FETs) with a double-independent-gate (DIG) structure for polarity control. Several structures are fabricated, showing the effec ...

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying ...

An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a ...

This paper presents a wireline serial data transceiver (TRX) architecture employing a concept of single-sideband (SSB) modulation to transmit data over a multi-drop (MD) electrical link with deep notches. The proposed TRX utilizes channel notch as a filter ...

This paper presents a new approach for monitoring and estimating device reliability of nanometer-scale devices prior to fabrication. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. A complete tool for ...

The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS cir ...

Yusuf Leblebici

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Multi-Camera Platform for Panoramic Real-Time HDR Video Construction and Rendering

Programmable Logic Circuits based on Ambipolar CNFET

Small signal analysis of electrically-stressed oxides with Poisson-Schroedinger based multiphonon capture model

Parallel vs. Serial Inter-plane communication using TSVs

Load optimization of an inductive power link for remote powering of biomedical implants

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

Ambipolar Si Nanowire Field Effect Transistors for Low Current and Temperature Sensing

Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications

Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Using 3D Integration Technology To Realize Multi-Context Fpgas

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Architectural Modeling of a Single-Sideband Wireline Serial Data Transceiver for Multi-Drop I/O

A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance Analysis

Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems