Publications de Christian Enz | EPFL Graph Search

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For a 4T pixel-based CMOS image sensors (CIS) readout chain, with column-level amplification and CDS, we show that the input-referred total noise in a standard 65 nm process can be reduced to 0.37 e-rms. Based on transient noise simulation using Eldo, the ...

This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a star ...

The recent advances made in MEMS and particularly in RF MEMS technology are enabling new architectures for the integration of RF transceivers with improved performance and smaller size. Several fundamental building blocks benefit from the availability of h ...

This paper introduces an approximate adder architecture based on a digital quasi-feedback technique called Carry Cut-Back in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach preve ...

We demonstrate cryogenic switching devices based on HEMT technology for scalable quantum computer (QC) control and readout signal routing. The switches are implemented in a quantum well network design without metal contacts between gates, and exhibit extre ...

This paper presents a noise reduction technique for Terahertz imaging based on modulating the THz source in order to transpose the signal at the output of the rectifier at a higher frequency where there is no 1/f noise and then filtering with a high Q bandpass filter centred at the modulation frequency. The filtering circuit, based on a 16-path passive switched capacitor (SC) bandpass filter, is modeled analytically. The presented technique is implemented in a test chip with a 130 nm process. Measurement re

A non-quasi-static (NQS) thermal noise model of the MOS transistor is presented that is valid in all modes of operation, from weak to strong inversion, and up to frequencies which are near or above the NQS cut-off frequency. It is shown that in addition to the well known induced gate noise (IGN) there is also an induced substrate noise that is generated and that the source and drain noises are also affected. All prior publications on the subject only deal with IGN in the strong inversion regime. It is shown

A 4 GHz, 100 kb/s FM-UWB transceiver for short-range communications in a body area network is presented. Two receivers and a transmitter use the same RF port with a fully-integrated matching network. The first receiver provides multi-user communication cap ...

In this paper a commercial 28 nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device-phys ...

Optical blood glucose sensing offers pain-free, non-invasive, continuous monitoring with minimum risk of infection since it does not require breaking the skin barrier. Among various optical detection and spectroscopic techniques, only Raman scattering offe ...

The Gm/ID approach has proven to be an efficient technique for the design of low-power analog circuits even in advanced technology nodes. It has already been shown that the normalized Gm/ID is actually a universal figure-of-merit (FoM) that is independent ...

The recently proposed BSIM6 bulk MOSFET compact model is set to replace the hitherto widely used BSIM3 and BSIM4 models as the de-facto industrial standard. Unlike its predecessors which were threshold voltage based, the BSIM6 core is charge based and thus ...

A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility. Their design highlights the tradeoff between performance, lifetime, cost, and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation). These considerations are illustra

A CMOS low-noise amplifier (LNA) with two variable gain ranges of 6 and 9 dB is presented. Variable gain is realized by using linearized MOS resistive circuits (MRCs) as voltage-controlled resistors. One of these resistors is located in the feedback loop of a transresistance output stage and the other is in the bias current generator of the transconductance input stage. Using compatible lateral bipolar transistors (CLBTs) in the fully differential transconductance input stage, the circuit takes advantage of

In this paper, the total ionizing dose (TID) response of a commercial 28-nm high-k CMOS technology at ultrahigh doses is measured and discussed. The degradation of pMOSFETs depends not only on the channel width but also on the channel length. Short-channel ...

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is dev ...

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capac ...

The Ward-Dutton (WD) partitioning scheme [IEEE Trans. Electron Devices, vol. ED-27, p. 1571, Aug. 1980] is used extensively to develop transient and high-frequency advanced compact models for MOSFET devices. Recently, it has been shown that WD partitioning ...

This paper presents a new radio architecture targeting RF transceivers for WSN, WBAN, and biomedical applications. The high miniaturization required by such applications is achieved thanks to the combination of high-Q MEMS devices, such as RF BAW re ...

Christian Enz

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Sub-electron CIS noise analysis in 65 nm process

A 51.4 Mb/s FSK Transmitter Employing a Phase Domain Digital Synthesizer with 1.5 mu s Start-up for Energy Efficient Duty Cycling

Building Blocks for an Ultra Low-Power MEMS-based Radio

A Low-power Carry Cut-Back Approximate Adder with Fixed-point Implementation and Floating-point Precision

Cryogenic InGaAs HEMT-Based Switches For Quantum Signal Routing

A noise reduction circuit technique for CMOS terahertz imaging

Non-Quasi-Static (NQS) Thermal Noise Modelling of the MOS Transistor

A 100 kb/s, 4 GHz, 267 mu W Fully Integrated Low Power FM-UWB Transceiver with Multiple Channels

Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing

Rapid, Sensitive and Selective Optical Glucose Sensing with Stimulated Raman Scattering (SRS)

Design of Cryo-CMOS Analog Circuits using the Gm/ID Approach

Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model

An Ultralow-Power UHF Transceiver Integrated in a Standard Digital CMOS Process: Architecture and Receiver

A Low Noise Amplifier with Automatic Gain Control and Anticlipping Control in CMOS Technology

Noise Modeling Methodologies in the Presence of Mobility Degradation and their Equivalence

Influence of Halo Implantations on the Total Ionizing Dose Response of 28-nm pMOSFETs Irradiated to Ultrahigh Doses

Cryogenic MOS Transistor Model

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Source–Drain Partitioning in MOSFET

A Narrowband Multi-Channel 2.4 GHz MEMS-Based Transceiver