Sub-electron CIS noise analysis in 65 nm process

For a 4T pixel-based CMOS image sensors (CIS) readout chain, with column-level amplification and CDS, we show that the input-referred total noise in a standard 65 nm process can be reduced to 0.37 e-rms. Based on transient noise simulation using Eldo, the deep sub-electron noise performance have been reached using only circuit techniques and optimal device choices. The simulation results have been favorably compared with analytical noise calculations. The shot noise associated to the gate tunneling current has been simulated and the possibility of photoelectron counting in this 65 nm process has been demonstrated.