Concept

Jeu d'instructions x86

Le jeu d'instructions du x86 a subi de nombreux changements au cours du temps. La plupart d'entre eux ne sont que des ajouts au jeu d'instructions initial afin d'apporter de nouvelles fonctionnalités. Ceci est le jeu d'instructions complet pour les processeurs 8086-8088 et la plupart, si ce n'est toutes ces instructions sont accessibles en mode 32 bits. Elles opèrent alors sur les registres et valeurs (eax, ebx, etc.) en lieu et place de leur contrepartie en (ax, bx, etc.). BOUND, ENTER, INSB, INSW, LEAVE, OUTSB, OUTSW, POPA, PUSHA, PUSHW ARPL, CLTS, LAR, LGDT, LIDT, LLDT, LMSW, LOADALL, LSL, LTR, SGDT, SIDT, SLDT, SMSW, STR, VERR, VERW BSF, BSR, BT, BTC, BTR, BTS, CDQ, CMPSD, CWDE, INSD, IRETD, IRETDF, IRETF, JECXZ, LFS, LGS, LSS, LODSD, LOOPD, LOOPED, LOOPNED, LOOPNZD, LOOPZD, MOVSD, MOVSX, MOVZX, OUTSD, POPAD, POPFD, PUSHAD, PUSHD, PUSHFD, SCASD, SETA, SETAE, SETB, SETBE, SETC, SETE, SETG, SETGE, SETL, SETLE, SETNA, SETNAE, SETNB, SETNBE, SETNC, SETNE, SETNG, SETNGE, SETNL, SETNLE, SETNO, SETNP, SETNS, SETNZ, SETO, SETP, SETPE, SETPO, SETS, SETZ, SHLD, SHRD, STOSD BSWAP, CMPXCHG, CPUID, INVD, INVLPG, RSM, WBINVD, XADD CMPXCHG8B, RDMSR, RDPMC*, RDTSC, WRMSR RDPMC a été introduit avec le processeur Pentium Pro et le processeur Pentium MMX CMOVA, CMOVAE, CMOVB, CMOVB, CMOVE, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNAE, CMOVNB, CMOVNBE, CMOVNC, CMOVNE, CMOVNG, CMOVNGE, CMOVNL, CMOVNLE, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVPE, CMOVPO, CMOVS, CMOVZ, SYSENTER, SYSEXIT, UD2 SYSCALL - Fonctionnalité spécifique au processeur AMD équivalente à l'instruction SYSENTER. SYSRET - Fonctionnalité spécifique au processeur AMD équivalente à l'instruction SYSEXIT.

Source officielle

https://fr.wikipedia.org/wiki/Jeu_d'instructions_x86

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Source officielle

https://fr.wikipedia.org/wiki/Jeu_d'instructions_x86

À propos de ce résultat

Cours associés (25)

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Paolo Ienne

Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.

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Mode virtuel 8086

Le mode virtuel 8086 () est un mode d'exécution particulier pour les processeurs de la famille x86. Ce mode fut créé avec l'apparition du processeur Intel 80386 en 1985 et est disponible sur toutes les versions ultérieures des processeurs Intel de la famille x86. Le mode virtuel 8086, aussi appelé Virtual 8086 ou V86, permet au processeur de se comporter comme un processeur 8086 ou 8088 pour lesquels n'existait que le mode réel.

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Compare-and-swap (CAS) est une instruction atomique utilisée dans les systèmes multiprocesseurs ou multi-cœurs utilisant une mémoire partagée. Elle compare la valeur stockée à une adresse mémoire donnée à l'un de ses arguments et, en cas d'égalité, écrit une nouvelle valeur à cette adresse. Selon les implémentations, elle signale si l'écriture a réussi soit en renvoyant une valeur booléenne, soit en renvoyant la valeur lue en mémoire.

Anneau de protection

Un anneau de protection (ring en anglais) est l’un des niveaux de privilèges imposés par l’architecture d’un processeur. De nombreuses architectures modernes de processeurs (architectures parmi lesquelles on trouve le populaire Intel x86) incluent une certaine forme de protection en anneau, bien que les logiciels d’exploitation ne l’exploitent pas toujours entièrement. Les rings étaient parmi les concepts les plus révolutionnaires mis en œuvre par le système d’exploitation Multics, un prédécesseur fortement sécurisé de la famille actuelle des systèmes d’exploitation UNIX.

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